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<p>Processing large amounts of data at high speed requires high-performance implementations of cryptographic modules. One of the most commonly used functions in authentication modules is the Keccak Secure Hash Algorithm-3 (SHA-3). Thanks to its resistance against recent attacks on older hashing functions, this algorithm was standardized by the National Institute of Standards and Technology (NIST) in 2012 after a selection contest. This work presents an efficient and high-frequency implementation of the SHA-3 hashing standard, focusing on increasing the maximum frequency while keeping resource consumption low. This goal is achieved through a well-designed control path that allows, on one hand, processing five messages successively in a five-stage pipeline with a one-clock cycle delay. The pipeline is accomplished by introducing registers between restructured subfunctions of the Keccak permutation function. On the other hand, the control path allows to generate outputs in the different sizes offered by SHA-3 variants. The proposed design achieves a maximum frequency of 676.18 MHz and a maximum throughput of 27.82 Gbps.</p>

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High throughput pipelined implementation of SHA3 hash algorithm on FPGA

  • 期刊论文

  • 发表日期：

    2025年5月28日

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  • Akram Kermiche,
  • Mohamed Saoudi,
  • Amine Drouiche

摘要

Processing large amounts of data at high speed requires high-performance implementations of cryptographic modules. One of the most commonly used functions in authentication modules is the Keccak Secure Hash Algorithm-3 (SHA-3). Thanks to its resistance against recent attacks on older hashing functions, this algorithm was standardized by the National Institute of Standards and Technology (NIST) in 2012 after a selection contest. This work presents an efficient and high-frequency implementation of the SHA-3 hashing standard, focusing on increasing the maximum frequency while keeping resource consumption low. This goal is achieved through a well-designed control path that allows, on one hand, processing five messages successively in a five-stage pipeline with a one-clock cycle delay. The pipeline is accomplished by introducing registers between restructured subfunctions of the Keccak permutation function. On the other hand, the control path allows to generate outputs in the different sizes offered by SHA-3 variants. The proposed design achieves a maximum frequency of 676.18 MHz and a maximum throughput of 27.82 Gbps.