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<p>This paper presents a low-complexity, high-performance ternary Full Adder (TFA) using carbon nanotube field-effect transistor (CNTFET) technology. The proposed design leverages unary operators, multiplexers, and a carry-less ternary half adder (THA) to achieve significant improvements in power efficiency and scalability. By employing a dual power supply, the design minimizes short-circuit power dissipation and reduces the transistor count to just 75 CNTFETs—one of the most compact TFA implementations to date. Simulated in HSPICE using the Stanford 32-nm CNTFET model, the proposed TFA demonstrates 32.41% lower power consumption, 23.39% lower energy, and competitive delay compared to the best state-of-the-art designs. Monte-Carlo analysis confirms robustness under process variations, with the lowest variability in power (0.024), delay (0.017), and energy (0.0298). To validate scalability, the TFA is extended to a 3-trit ripple carry adder (RCA), achieving 36.04% lower power and 30.2% lower energy than prior work. This work advances ternary logic systems by offering a compact, energy-efficient solution for next-generation arithmetic circuits, with potential applications in AI hardware, low-power processors, and beyond-binary computing.</p>

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Low Complexity, High-Performance Ternary Full Adder Using CNTFET Technology

  • 期刊论文

  • 发表日期：

    2026年1月29日

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  • Km Umaira Dilshad,
  • Shams Ul Haq,
  • Erfan Abbasian,
  • Sajad A. Loan

摘要

This paper presents a low-complexity, high-performance ternary Full Adder (TFA) using carbon nanotube field-effect transistor (CNTFET) technology. The proposed design leverages unary operators, multiplexers, and a carry-less ternary half adder (THA) to achieve significant improvements in power efficiency and scalability. By employing a dual power supply, the design minimizes short-circuit power dissipation and reduces the transistor count to just 75 CNTFETs—one of the most compact TFA implementations to date. Simulated in HSPICE using the Stanford 32-nm CNTFET model, the proposed TFA demonstrates 32.41% lower power consumption, 23.39% lower energy, and competitive delay compared to the best state-of-the-art designs. Monte-Carlo analysis confirms robustness under process variations, with the lowest variability in power (0.024), delay (0.017), and energy (0.0298). To validate scalability, the TFA is extended to a 3-trit ripple carry adder (RCA), achieving 36.04% lower power and 30.2% lower energy than prior work. This work advances ternary logic systems by offering a compact, energy-efficient solution for next-generation arithmetic circuits, with potential applications in AI hardware, low-power processors, and beyond-binary computing.