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<p>Low-noise amplifiers (LNAs) are pivotal in modern wireless communication systems, particularly for Extremely High-Throughput (EHT) applications. It faces a significant challenge in balancing gain, power consumption, noise figure (NF), and linearity across wide operating frequency ranges, which hampers EHT system performance. Recent techniques, including inductive degeneration, feedback networks, and cascode structures, have addressed some of these challenges. However, it often introduces trade-offs in power efficiency or linearity, limiting their applicability for next-generation systems. To address these issues, this paper proposes a novel common gate–common source–common source (CG–CS<sup>2</sup>) low-noise amplifier with an optimal matching network to enhance gain, power efficiency, and linearity simultaneously. The design incorporates a CS stage with a PMOS current source into the conventional CG–CS amplifier, inspired by the multi-gate transistor technique. This modification reduces the NF by 0.53&#xa0;dB and improves the third-order input intercept point (IIP3) by 6.435&#xa0;dBm without the additional power consumption, and it is implemented in Cadence UMC 65&#xa0;nm technology with a 1.2&#xa0;V supply. The CG–CS<sup>2</sup> LNA achieves a gain and NF of 16.21/19.1&#xa0;dB and 3.97/4.5&#xa0;dB with/without an additional CS amplifier while consuming only 3mW. The proposed single-differential LNA, operating within 2.37–6.7&#xa0;GHz and achieving S11 &lt; − 10&#xa0;dB, is ideal for EHT applications requiring high linearity and low power.</p>

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Power-Efficient Modified Multi-Gate High-Linear LNA for EHT Wireless Applications

  • 期刊论文

  • 发表日期：

    2025年7月30日

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  • Thenmozhi V,
  • M. Bhaskar

摘要

Low-noise amplifiers (LNAs) are pivotal in modern wireless communication systems, particularly for Extremely High-Throughput (EHT) applications. It faces a significant challenge in balancing gain, power consumption, noise figure (NF), and linearity across wide operating frequency ranges, which hampers EHT system performance. Recent techniques, including inductive degeneration, feedback networks, and cascode structures, have addressed some of these challenges. However, it often introduces trade-offs in power efficiency or linearity, limiting their applicability for next-generation systems. To address these issues, this paper proposes a novel common gate–common source–common source (CG–CS2) low-noise amplifier with an optimal matching network to enhance gain, power efficiency, and linearity simultaneously. The design incorporates a CS stage with a PMOS current source into the conventional CG–CS amplifier, inspired by the multi-gate transistor technique. This modification reduces the NF by 0.53 dB and improves the third-order input intercept point (IIP3) by 6.435 dBm without the additional power consumption, and it is implemented in Cadence UMC 65 nm technology with a 1.2 V supply. The CG–CS2 LNA achieves a gain and NF of 16.21/19.1 dB and 3.97/4.5 dB with/without an additional CS amplifier while consuming only 3mW. The proposed single-differential LNA, operating within 2.37–6.7 GHz and achieving S11 < − 10 dB, is ideal for EHT applications requiring high linearity and low power.