<p>This paper presents a hybrid RRAM/FinFET ternary architecture, showcasing its versatility in executing diverse ternary logic operations. Introducing a novel polymorphic ternary gate, the design seamlessly handles all 2-input primitive ternary logic gates. In an elegant fusion with a reconfigurable array architecture, the paper presents the implementation of a ternary half adder, ternary full adder, ternary comparator, and ternary multiplier. The proposed design's performance is meticulously examined through HSPICE simulations, revealing remarkable power-delay product (PDP) reductions. Specifically, the PDP achieves a 24%, 49%, 50%, and 51% decrease compared to the benchmark structure for the half adder, full adder, multiplier, and comparator. Taking innovation a step further, the paper evaluates the practical application of the architecture in real-world scenarios. A noise reduction method, serving as the preprocessing stage for edge detection and a convolutional ternary neural network (TNN), is implemented using the proposed architecture. The outcomes are striking, demonstrating 51% and 70% improvements in the energy consumption of the ternary noise reduction and TNN implemented using the proposed method.</p>