Scholarlink

<p>This paper presents post-layout analysis of a modified 64-bit Priority Encoder (PE) design optimized for speed and efficiency. Our previous research implemented a scalable 1D-to-2D array conversion technique for PE implementation, demonstrating its effectiveness in 4-bit, 16-bit, and 64-bit designs. Here, we extend this approach by analyzing the post-layout performance of a 1V 64-bit PE fabricated in an 180&#xa0;nm CMOS process. Compared to a reference design, our post-layout simulations reveal a significant 47.37% improvement in operating frequency. This remarkable enhancement highlights the robustness and efficiency of our proposed PE architecture, making it particularly suitable for high-speed data processing applications.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Performance analysis of 1D-to-2D array conversion for priority encoders in post-layout design

  • 期刊论文

  • 发表日期：

    2025年7月8日

查看全文
  • Dhandapani Vaithiyanathan,
  • Abhishek Behera,
  • Alok Kumar Mishra,
  • Preeti Verma

摘要

This paper presents post-layout analysis of a modified 64-bit Priority Encoder (PE) design optimized for speed and efficiency. Our previous research implemented a scalable 1D-to-2D array conversion technique for PE implementation, demonstrating its effectiveness in 4-bit, 16-bit, and 64-bit designs. Here, we extend this approach by analyzing the post-layout performance of a 1V 64-bit PE fabricated in an 180 nm CMOS process. Compared to a reference design, our post-layout simulations reveal a significant 47.37% improvement in operating frequency. This remarkable enhancement highlights the robustness and efficiency of our proposed PE architecture, making it particularly suitable for high-speed data processing applications.