<p>For the VLSI circuit to be designed, floor planning is essential. Since floor planning describes the size, shape, and locations of modules on a chip, it is a critical design step in VLSI physical design since it estimates the chip's overall area, interconnects, and latency. A well-thought-out floor layout results in an ASIC design with increased performance and the ideal amount of space. Effective floor plan optimization is required to improve performance and lower resource consumption due to the growing complexity of VLSI circuit designs. Inefficiencies result from traditional optimization techniques' inability to balance several goals, such as wire length reduction and area minimization. In order to overcome these drawbacks, this work presents the Combined FAT and Chimp Algorithm (CFAT-CA), an innovative hybrid optimization strategy that integrates standard CO and FAT. Numerous objectives are taken into consideration, including area, penalty function, and wire length. The layout takes up less room due to wire length and optimal area estimation. Consequently, there is less layout area. The effectiveness of the predicted model in lowering the area associated with floor planning is validated by analysis of the suggested CFAT-CA-based multi-objective model. The proposed model has attained the FIR filter's minimum overlap value, which was very nearly zero, when compared to existing state of art models.</p>