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<p>Partitioning plays an essential role in the design of VLSI circuits. With the increase in the size and type of the design, the need for practical partitioning tools is increasing rapidly. The design process involving physical partitioning of VLSI systems consists of many complexities due to the rapidly changing design requirements and specifications. These dynamic changes have reiterated the essentiality of good partitioning tools in the future. The design of VLSI systems incorporates millions of transistors and semiconductors, and simulating such systems becomes a complex task. To overcome this, the circuit is split into multiple subsystems to obtain a compact system, using appropriate partitioning tools. This paper introduces a circuit partitioning methodology employing the graph cellular automata (GCA) algorithm, aimed at reducing latency, area, interconnect length, and cut size. The proposed approach scales better for large hypergraphs. Results show that the proposed GCA is speedy with lesser time complexity, often requiring less time than other techniques. A comparative analysis is carried out to investigate the performance of the GCA approach compared to existing optimized circuit partitioning techniques following the ISCAS'85 Verilog netlist. Experimental results show that GCA provides more accurate circuit partitioning than existing techniques.</p>

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Cellular automata-based framework for yield optimization in VLSI physical design of large-scale benchmark circuits

  • 期刊论文

  • 发表日期：

    2025年7月9日

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  • R. Pavithra Guru,
  • V. Vaithianathan

摘要

Partitioning plays an essential role in the design of VLSI circuits. With the increase in the size and type of the design, the need for practical partitioning tools is increasing rapidly. The design process involving physical partitioning of VLSI systems consists of many complexities due to the rapidly changing design requirements and specifications. These dynamic changes have reiterated the essentiality of good partitioning tools in the future. The design of VLSI systems incorporates millions of transistors and semiconductors, and simulating such systems becomes a complex task. To overcome this, the circuit is split into multiple subsystems to obtain a compact system, using appropriate partitioning tools. This paper introduces a circuit partitioning methodology employing the graph cellular automata (GCA) algorithm, aimed at reducing latency, area, interconnect length, and cut size. The proposed approach scales better for large hypergraphs. Results show that the proposed GCA is speedy with lesser time complexity, often requiring less time than other techniques. A comparative analysis is carried out to investigate the performance of the GCA approach compared to existing optimized circuit partitioning techniques following the ISCAS'85 Verilog netlist. Experimental results show that GCA provides more accurate circuit partitioning than existing techniques.