Conventional silicon-based tunneling field-effect transistors (TFETs) face several issues, including limited ON current, ambipolar conduction, and suboptimal RF performance. This simulation-based study presents a detailed design and optimization approach for a high-performance heterostructure nanowire tunneling FET (NW-TFET). Starting from a fabricated baseline NW-TFET structure, we modify the design through a series of optimization phases to improve both DC and radio-frequency (RF) characteristics. The proposed design features a heterojunction structure in which the source region is composed of Si1-xGex to enhance the tunneling probability, thereby increasing the ON current. The design also includes the integration of a 15 nm HfO2 pocket, careful tuning of gate-source alignment, and optimization of the x-composition in the source. Extensive simulations show significant improvements in ON current (ION), ON/OFF current ratio, subthreshold swing, and cutoff frequency (<InlineEquation ID="IEq1"> <EquationSource Format="TEX">${f}_{T})$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <msub> <mi>f</mi> <mi>T</mi> </msub> <mrow> <mo stretchy="false">)</mo> </mrow> </mrow> </math></EquationSource> </InlineEquation> compared to the initial configuration, with x = 0.75, 0.5 nm pocket underlap, 50 nm gate length, <InlineEquation ID="IEq2"> <EquationSource Format="TEX">$60\text{ nm}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>60</mn> <mspace width="0.333333em" /> <mtext>nm</mtext> </mrow> </math></EquationSource> </InlineEquation> channel length and work function of 4.3 eV. The optimized device achieves an ON/OFF ratio of 4.79 × 106, a subthreshold swing (SS) of 64.5 mV/decade, threshold voltage (<InlineEquation ID="IEq3"> <EquationSource Format="TEX">${V}_{t})$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <msub> <mi>V</mi> <mi>t</mi> </msub> <mrow> <mo stretchy="false">)</mo> </mrow> </mrow> </math></EquationSource> </InlineEquation> of 0.253 V and a maximum cutoff frequency of 355 GHz, while keeping ambipolar current low. These findings highlight the potential of the proposed NW-TFET architecture for low-power, high-speed applications.

Numerical Simulation Study and Design Optimization of High-Performance SiGe/Si Heterostructure Nanowire Tunnel FETs

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2026年1月20日

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Mina Labib,
Ahmed Shaker,
Michael Gad,
Yasmine Elogail

摘要

Conventional silicon-based tunneling field-effect transistors (TFETs) face several issues, including limited ON current, ambipolar conduction, and suboptimal RF performance. This simulation-based study presents a detailed design and optimization approach for a high-performance heterostructure nanowire tunneling FET (NW-TFET). Starting from a fabricated baseline NW-TFET structure, we modify the design through a series of optimization phases to improve both DC and radio-frequency (RF) characteristics. The proposed design features a heterojunction structure in which the source region is composed of Si_1-xGe_x to enhance the tunneling probability, thereby increasing the ON current. The design also includes the integration of a 15 nm HfO₂ pocket, careful tuning of gate-source alignment, and optimization of the x-composition in the source. Extensive simulations show significant improvements in ON current (I_ON), ON/OFF current ratio, subthreshold swing, and cutoff frequency ( ${f}_{T})$ $f_{T})$ compared to the initial configuration, with x = 0.75, 0.5 nm pocket underlap, 50 nm gate length, $60\text{ nm}$ $60 nm$ channel length and work function of 4.3 eV. The optimized device achieves an ON/OFF ratio of 4.79 × 10⁶, a subthreshold swing (SS) of 64.5 mV/decade, threshold voltage ( ${V}_{t})$ $V_{t})$ of 0.253 V and a maximum cutoff frequency of 355 GHz, while keeping ambipolar current low. These findings highlight the potential of the proposed NW-TFET architecture for low-power, high-speed applications.