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<p>The growing demand for portable biomedical devices necessitates the use of on-chip memory, specifically SRAM cells, to strengthen system performance, especially for the applications like insulin pumps, biosensing devices, pacemakers, electrocardiogram (ECG) devices and IoT-enabled wearable biomedical electronics often referred to the internet of bio-nano-things (IoBNT), where power overuse and draining is a significant constraint. The conventional 6 Transistors memory design is ideal for rapid responsive and tiny size memory circuits, but it struggles to obtain greater read stability and low power dissipation when scaling, leading to supply voltage scaling. Alternatively, Researchers propose various memory cell architectures ranging from 7 to 12&#xa0;T ensuring low power consumption and condensed leakage currents, but none meet optimum power constraints. The proliferating desire for the power-efficient circuits necessitates a substantial mitigation in leaky current in the implementation of any IC. FinFET technology offers increased gate regulation over the channel, mitigating the leakage by altering the threshold voltage and becoming a scaled alternative to CMOS. The research paper introduces a faster and more power efficient FINFET-based Intramural loop 7&#xa0;T (IL7T) SRAM architecture, which adopted self-controllable voltage level (SVL) approaches to further mitigate leakage power. This research focuses on designing of a SRAM Architecture based on 18&#xa0;nm FinFET using SVL approach to optimize leaky current and power to a desire level. The proposed design utilizes the combined SVL technique, achieves a minimal leakage current and power of 14.69 nA and 10.2 nW respectively. The schematics implementation and simulation were conducted using 18&#xa0;nm FinFET technology library node in cadence virtuoso environment at the operating voltage or supply voltage of 0.7&#xa0;V.</p>

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Improved Leaky Mitigation in an IL7T SRAM Cell Based on FinFET Using SVL Approach for Portable Biomedical Equipment

  • 期刊论文

  • 发表日期：

    2025年12月13日

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  • Lal John Basha Shaik,
  • Atul Shankar Mani Tripathi

摘要

The growing demand for portable biomedical devices necessitates the use of on-chip memory, specifically SRAM cells, to strengthen system performance, especially for the applications like insulin pumps, biosensing devices, pacemakers, electrocardiogram (ECG) devices and IoT-enabled wearable biomedical electronics often referred to the internet of bio-nano-things (IoBNT), where power overuse and draining is a significant constraint. The conventional 6 Transistors memory design is ideal for rapid responsive and tiny size memory circuits, but it struggles to obtain greater read stability and low power dissipation when scaling, leading to supply voltage scaling. Alternatively, Researchers propose various memory cell architectures ranging from 7 to 12 T ensuring low power consumption and condensed leakage currents, but none meet optimum power constraints. The proliferating desire for the power-efficient circuits necessitates a substantial mitigation in leaky current in the implementation of any IC. FinFET technology offers increased gate regulation over the channel, mitigating the leakage by altering the threshold voltage and becoming a scaled alternative to CMOS. The research paper introduces a faster and more power efficient FINFET-based Intramural loop 7 T (IL7T) SRAM architecture, which adopted self-controllable voltage level (SVL) approaches to further mitigate leakage power. This research focuses on designing of a SRAM Architecture based on 18 nm FinFET using SVL approach to optimize leaky current and power to a desire level. The proposed design utilizes the combined SVL technique, achieves a minimal leakage current and power of 14.69 nA and 10.2 nW respectively. The schematics implementation and simulation were conducted using 18 nm FinFET technology library node in cadence virtuoso environment at the operating voltage or supply voltage of 0.7 V.