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<p>Amid the quest for ultra-low power nano scaled devices to mimic the biological neuronal functionalities, this article presents a reconfigurable L-shaped double gate (RL-DG) MOSFET for the realization of spiking neural network (SNN). Using well-calibrated 2D TCAD simulations, both the synaptic and neuronal functionalities of the device have been explored by reconfiguring the front and the back gate respectively. The front gate and the oxide/nitride/oxide (O/N/O) stack is used to imitate the synaptic dynamics while the back gate with unique feature of L-shape offers high rate of impact ionization to emulate the leaky integration behavior. Biological synapse realization of the present device is investigated in terms of paired-pulse facilitation/depression (PPF/PPD). The proposed RL-DG MOSFET when configured as leaky–integrate and fire (LIF) neuron consumes 619.5 fJ energy per spike which is much lower as compared to PD SOI LIF neuron and some of the recently published BTBT, FinFET and FB based neurons. In addition, it also exhibits a higher spiking frequency (in the range of gigahertz) ∼8 order greater than the biological neuron, low threshold voltage of 0.086&#xa0;V and reduced breakdown voltage of 0.48&#xa0;V, due to crowding of the electric field lines near the gate edges. The results obtained presume that the proposed L-shaped DG MOSFET with reconfigurable functionality of synapse and neuronal behavior will be a potential candidate for hardware implementation of SNN owing to its ultra-low power energy efficiency and CMOS compatibility.</p>

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Design of Reconfigurable Spiking Neurosynaptic Transistor for Spiking Neural Network Using L- Shaped DG MOSFET

  • 期刊论文

  • 发表日期：

    2025年11月15日

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  • Saheli Sarkhel,
  • Tripty Kumari,
  • Rittik Ghosh,
  • Priyanka Saha

摘要

Amid the quest for ultra-low power nano scaled devices to mimic the biological neuronal functionalities, this article presents a reconfigurable L-shaped double gate (RL-DG) MOSFET for the realization of spiking neural network (SNN). Using well-calibrated 2D TCAD simulations, both the synaptic and neuronal functionalities of the device have been explored by reconfiguring the front and the back gate respectively. The front gate and the oxide/nitride/oxide (O/N/O) stack is used to imitate the synaptic dynamics while the back gate with unique feature of L-shape offers high rate of impact ionization to emulate the leaky integration behavior. Biological synapse realization of the present device is investigated in terms of paired-pulse facilitation/depression (PPF/PPD). The proposed RL-DG MOSFET when configured as leaky–integrate and fire (LIF) neuron consumes 619.5 fJ energy per spike which is much lower as compared to PD SOI LIF neuron and some of the recently published BTBT, FinFET and FB based neurons. In addition, it also exhibits a higher spiking frequency (in the range of gigahertz) ∼8 order greater than the biological neuron, low threshold voltage of 0.086 V and reduced breakdown voltage of 0.48 V, due to crowding of the electric field lines near the gate edges. The results obtained presume that the proposed L-shaped DG MOSFET with reconfigurable functionality of synapse and neuronal behavior will be a potential candidate for hardware implementation of SNN owing to its ultra-low power energy efficiency and CMOS compatibility.