<p>The growing dependence on the rise of hyper-personalized devices and artificial intelligence has significantly increased the demand for faster static random access memory (SRAM) for users. The complementary metal-oxide-semiconductor (CMOS) sense amplifier is a critical component in SRAM cells, playing a pivotal role in reading and retrieving stored data. The CMOS sense amplifier is essential for overcoming noise and ensuring reliable and accurate retrieval of data during read operations of memory cells. Due to the usage of smaller nanoscale technologies and near-threshold voltage operations, the CMOS sense amplifier’s immunity also decreases. These low-immune circuits cause a soft error in logic transfer. Therefore, the tolerance of the CMOS sense amplifier to single-event upsets (SEUs) is an important consideration in small nanoscale technologies near the threshold voltage regime. This paper presents a faster and energy-efficient SEU tolerance-based circuit implemented on a latched-based sense amplifier design. We validated the proposed design in 90 nm CMOS technology and technology computer-aided design (TCAD)-calibrated 32 nm CMOS technology. The post-layout simulations show significant improvements in the proposed design. Specifically, at VDD = 0.5 V in 90 nm CMOS technology, there is an average enhancement of approximately 60, 59, and 36% in power dissipation, layout area and propagation delay, respectively, compared to the reported sense amplifier design. In TCAD-calibrated 32-nm CMOS technology, the design proposed in this paper demonstrates an improvement of 52 and 57% in power dissipation and propagation delay at VDD = 0.3 V over other sense amplifier designs.</p>