<p>An efficient and energy-aware arithmetic circuit is crucial in modern digital systems, especially in signal processing, cryptography, and embedded computing. Multipliers, a key component of arithmetic logic units (ALUs), directly impact computational speed and power efficiency. Conventional multipliers based on irreversible logic lead to excessive power dissipation due to information loss. This paper addresses the above challenges by introducing three optimized reversible vedic multiplier designs that integrate BME, improved Peres, and hybrid gates to enhance performance. These architectures effectively reduce quantum cost (QC), garbage outputs (GO), and total reversible logic implementation cost (TRLIC), improving power efficiency. The designs are implemented and synthesized using Cadence 180 nm EDA tools and Xilinx ISE 14.7, ensuring feasibility for FPGA-based applications. The performance evaluation across <InlineEquation ID="IEq1"> <EquationSource Format="TEX">$2\times 2$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>2</mn> <mo>×</mo> <mn>2</mn> </mrow> </math></EquationSource> </InlineEquation>, <InlineEquation ID="IEq2"> <EquationSource Format="TEX">$4\times 4$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>4</mn> <mo>×</mo> <mn>4</mn> </mrow> </math></EquationSource> </InlineEquation>, <InlineEquation ID="IEq3"> <EquationSource Format="TEX">$8\times 8$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>8</mn> <mo>×</mo> <mn>8</mn> </mrow> </math></EquationSource> </InlineEquation>, <InlineEquation ID="IEq4"> <EquationSource Format="TEX">$16\times 16$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>16</mn> <mo>×</mo> <mn>16</mn> </mrow> </math></EquationSource> </InlineEquation>, and <InlineEquation ID="IEq5"> <EquationSource Format="TEX">$32\times 32$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>32</mn> <mo>×</mo> <mn>32</mn> </mrow> </math></EquationSource> </InlineEquation>-bit multipliers demonstrates their scalability. The hybrid gate-based architecture is the most efficient choice for low-power, high-speed computing applications. It reduces the area by 14.1% and power consumption by 9.8% compared with the other two methods. The results show the scalability and adaptability of the proposed multipliers, making them suitable for ALU design, FPGA implementations, and quantum computing architecture.</p>

Quantum cost-optimized reversible vedic multipliers: A next-generation approach

期刊论文
发表日期：

2026年5月27日

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Rishu Yadav,
Nagendra Kushwaha,
Sandeep Mishra,
Ashish Ranjan

摘要

An efficient and energy-aware arithmetic circuit is crucial in modern digital systems, especially in signal processing, cryptography, and embedded computing. Multipliers, a key component of arithmetic logic units (ALUs), directly impact computational speed and power efficiency. Conventional multipliers based on irreversible logic lead to excessive power dissipation due to information loss. This paper addresses the above challenges by introducing three optimized reversible vedic multiplier designs that integrate BME, improved Peres, and hybrid gates to enhance performance. These architectures effectively reduce quantum cost (QC), garbage outputs (GO), and total reversible logic implementation cost (TRLIC), improving power efficiency. The designs are implemented and synthesized using Cadence 180 nm EDA tools and Xilinx ISE 14.7, ensuring feasibility for FPGA-based applications. The performance evaluation across $2\times 2$ $2 \times 2$ , $4\times 4$ $4 \times 4$ , $8\times 8$ $8 \times 8$ , $16\times 16$ $16 \times 16$ , and $32\times 32$ $32 \times 32$ -bit multipliers demonstrates their scalability. The hybrid gate-based architecture is the most efficient choice for low-power, high-speed computing applications. It reduces the area by 14.1% and power consumption by 9.8% compared with the other two methods. The results show the scalability and adaptability of the proposed multipliers, making them suitable for ALU design, FPGA implementations, and quantum computing architecture.