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<p>In this paper, simple topologies for implementing electronically tunable fractional-order inductors (FOIs) using second-generation current conveyors and a single capacitor have been proposed. The suggested topologies are compact in nature and consume less power. Different circuits for the design of grounded and floating inductors, along with the implementation of a negative fractional-order inductor, have been proposed. Results for inductors of orders 0.2, 0.5, and 0.8 have been discussed in detail. All simulations are carried out for 180 nm CMOS technology with ±1.2 V. A comprehensive analysis has been done to evaluate the performance of the proposed FOI. Frequency analysis has been performed along with a comparison with ideal responses. All of these findings attest to the proper operation of the proposed circuits. Phase response has been tested through transient analysis. Application of the proposed FOI is demonstrated through the implementation of <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(1+\alpha \)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>1</mn> <mo>+</mo> <mi>α</mi> </mrow> </math></EquationSource> </InlineEquation>-order band-pass filter. Comparative studies demonstrate the advantages of the proposed work and its effectiveness over existing approaches.</p>

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CCCII and DOCCCII-based electronically-tunable positive and negative fractional-order inductors

  • 期刊论文

  • 发表日期：

    2026年4月9日

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  • Ritu Daryani,
  • Bhawna Aggarwal

摘要

In this paper, simple topologies for implementing electronically tunable fractional-order inductors (FOIs) using second-generation current conveyors and a single capacitor have been proposed. The suggested topologies are compact in nature and consume less power. Different circuits for the design of grounded and floating inductors, along with the implementation of a negative fractional-order inductor, have been proposed. Results for inductors of orders 0.2, 0.5, and 0.8 have been discussed in detail. All simulations are carried out for 180 nm CMOS technology with ±1.2 V. A comprehensive analysis has been done to evaluate the performance of the proposed FOI. Frequency analysis has been performed along with a comparison with ideal responses. All of these findings attest to the proper operation of the proposed circuits. Phase response has been tested through transient analysis. Application of the proposed FOI is demonstrated through the implementation of \(1+\alpha \) 1 + α -order band-pass filter. Comparative studies demonstrate the advantages of the proposed work and its effectiveness over existing approaches.