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<p>In this article, electrostatic surface and bulk potential modeling of the pre- and post-snapback behavior of n-type field-effect transistor (<i>n</i>-FET)-based protection devices is derived under ultrafast current pulsing conditions. In the design of electrostatic discharge (ESD) protection devices, the relevant physical and analytical models are of the utmost importance. Therefore, the electrical characteristics of a gate-grounded N-channel metal–oxide–semiconductor (GG-NMOS) transistor under ESD pulsing conditions are physically and mathematically modeled for fast circuit simulation using the conformal mapping method with appropriate boundary conditions in all the regions of the <i>n</i>-FET structure. The closed-form expressions for the surface and bulk electrostatic potential and electric field before and after first snapback are compared with technology computer-aided design (TCAD) device simulation results, revealing good agreement between them. This work also demonstrates the process of bipolar turn-on through a device simulation tool and validates our proposed physical model with the derived analytical expressions. Further, the concept of current gain (i.e., β) is applied to describe the coupling of electron and hole injection and subsequently the role of bulk bipolar turn-on. Finally, the first snapback mechanism in the GG-NMOS is investigated with respect to different channel lengths.</p>

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Electrostatic Surface and Bulk Potential Modeling of Snapback Behavior of n-FET Protection Devices

  • 期刊论文

  • 发表日期：

    2026年5月26日

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  • Prabhat Kumar,
  • Dheeraj Kumar Sinha,
  • Sanjay Kumar

摘要

In this article, electrostatic surface and bulk potential modeling of the pre- and post-snapback behavior of n-type field-effect transistor (n-FET)-based protection devices is derived under ultrafast current pulsing conditions. In the design of electrostatic discharge (ESD) protection devices, the relevant physical and analytical models are of the utmost importance. Therefore, the electrical characteristics of a gate-grounded N-channel metal–oxide–semiconductor (GG-NMOS) transistor under ESD pulsing conditions are physically and mathematically modeled for fast circuit simulation using the conformal mapping method with appropriate boundary conditions in all the regions of the n-FET structure. The closed-form expressions for the surface and bulk electrostatic potential and electric field before and after first snapback are compared with technology computer-aided design (TCAD) device simulation results, revealing good agreement between them. This work also demonstrates the process of bipolar turn-on through a device simulation tool and validates our proposed physical model with the derived analytical expressions. Further, the concept of current gain (i.e., β) is applied to describe the coupling of electron and hole injection and subsequently the role of bulk bipolar turn-on. Finally, the first snapback mechanism in the GG-NMOS is investigated with respect to different channel lengths.