Scholarlink

<p>This study reports, for the first time, the coupled failure phenomenon in monolithically integrated gallium nitride (GaN) power chips under load dump stress. Experimental results show that when stress is applied to the drain terminal of the high-side device in a half-bridge integrated chip, the high-side device exhibits a positive threshold voltage shift and on-state current degradation, while the low-side device simultaneously demonstrates threshold voltage drift and current characteristic deterioration. The underlying mechanism originates from the floating substrate configuration: under high-side stress, electrons and holes accumulate in the substrate layer at the drain of the high-side device and the region of the low-side device, respectively, creating a high potential in the low-side substrate. This induces electron trapping in the buffer layer, ultimately leading to an increased threshold voltage and reduced conduction current in the low-side device. In contrast, when stress is applied to the low-side drain, the charges generated in the low-side substrate can be effectively dissipated through its source-grounded path, thereby significantly mitigating coupling interference to the high-side device. Notably, devices under <i>V</i><sub>GS</sub> = 1.6&#xa0;V and <i>V</i><sub>GS</sub> = 6&#xa0;V conditions face burnout risks under transient load dump stress. This occurs because a conductive path already exists between the drain and source, where the coexistence of transient high voltage and high current causes localized thermal accumulation, eventually resulting in catastrophic failure. The significance of this finding lies in providing important support for research on load dump failure in monolithically integrated GaN chips and directly contributing to the improvement of their application reliability.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Coupled Degradation Behavior in a Monolithically Integrated GaN Power Chip Under Load Dump Stress

  • 期刊论文

  • 发表日期：

    2026年2月4日

查看全文
  • Huangtao Zeng,
  • Chao Yang,
  • Zhiyuan He,
  • Yijun Shi,
  • Liang He,
  • Guoguang Lu,
  • Yuan Chen,
  • Xinghuan Chen,
  • Xianzhong Zhou,
  • Zhipeng Shen

摘要

This study reports, for the first time, the coupled failure phenomenon in monolithically integrated gallium nitride (GaN) power chips under load dump stress. Experimental results show that when stress is applied to the drain terminal of the high-side device in a half-bridge integrated chip, the high-side device exhibits a positive threshold voltage shift and on-state current degradation, while the low-side device simultaneously demonstrates threshold voltage drift and current characteristic deterioration. The underlying mechanism originates from the floating substrate configuration: under high-side stress, electrons and holes accumulate in the substrate layer at the drain of the high-side device and the region of the low-side device, respectively, creating a high potential in the low-side substrate. This induces electron trapping in the buffer layer, ultimately leading to an increased threshold voltage and reduced conduction current in the low-side device. In contrast, when stress is applied to the low-side drain, the charges generated in the low-side substrate can be effectively dissipated through its source-grounded path, thereby significantly mitigating coupling interference to the high-side device. Notably, devices under VGS = 1.6 V and VGS = 6 V conditions face burnout risks under transient load dump stress. This occurs because a conductive path already exists between the drain and source, where the coexistence of transient high voltage and high current causes localized thermal accumulation, eventually resulting in catastrophic failure. The significance of this finding lies in providing important support for research on load dump failure in monolithically integrated GaN chips and directly contributing to the improvement of their application reliability.