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<p>We present an innovative approach to enhance the short-circuit (SC) robustness of 1.2-kV planar gate SiC MOSFETs by optimizing the N-buffer ion implantation concentration distribution. Utilizing Sentaurus TCAD simulation, we investigate the effects of four distinct N-buffer doping profiles on both the static and short-circuit performance of SiC MOSFETs across varying JFET region widths (W<sub>JFET</sub>). As W<sub>JFET</sub> increases, the results show a consistent reduction in breakdown voltage, an initial rise followed by a decrease in peak SC current (I<sub>peak</sub>), and a continuous decrease in SC energy dissipation across all MOSFETs. The optimal Baliga’s figure-of-merit (BFOM) is achieved at W<sub>JFET</sub>&#xa0;=&#xa0;1.6&#xa0;<i>μ</i>m for all designs. Compared to the conventional uniform N-buffer, the other three configurations significantly enhance the SC capability. In particular, the ST-MOSFET exhibits an 8.7% improvement in short-circuit withstand time (SCWT) while preserving static characteristics. This enhancement is attributed to optimized potential distribution within the JFET region, which lowers current density and suppresses Joule heating. Meanwhile, the IT-MOSFET and PT-MOSFET improve SC performance by shifting the primary heat generation region away from the gate oxide. These insights are critical for the design of more reliable and robust SiC MOSFETs for power electronics applications.</p>

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Investigation on Improving Short-Circuit Characteristic of 1200-V Planar-Gate SiC MOSFETs Using Enhanced N-Buffer Design

  • 期刊论文

  • 发表日期：

    2025年11月3日

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  • Wenjing Zhang,
  • Yanjing He,
  • Guofeng Hu,
  • Hao Yuan,
  • Qingwen Song,
  • Lejia Sun,
  • Xiaowu Gong,
  • Yuming Zhang

摘要

We present an innovative approach to enhance the short-circuit (SC) robustness of 1.2-kV planar gate SiC MOSFETs by optimizing the N-buffer ion implantation concentration distribution. Utilizing Sentaurus TCAD simulation, we investigate the effects of four distinct N-buffer doping profiles on both the static and short-circuit performance of SiC MOSFETs across varying JFET region widths (WJFET). As WJFET increases, the results show a consistent reduction in breakdown voltage, an initial rise followed by a decrease in peak SC current (Ipeak), and a continuous decrease in SC energy dissipation across all MOSFETs. The optimal Baliga’s figure-of-merit (BFOM) is achieved at WJFET = 1.6 μm for all designs. Compared to the conventional uniform N-buffer, the other three configurations significantly enhance the SC capability. In particular, the ST-MOSFET exhibits an 8.7% improvement in short-circuit withstand time (SCWT) while preserving static characteristics. This enhancement is attributed to optimized potential distribution within the JFET region, which lowers current density and suppresses Joule heating. Meanwhile, the IT-MOSFET and PT-MOSFET improve SC performance by shifting the primary heat generation region away from the gate oxide. These insights are critical for the design of more reliable and robust SiC MOSFETs for power electronics applications.