Gate-induced drain leakage (GIDL) poses a critical challenge in scaled nanowire gate-all-around (GAA) metal–oxide–semiconductor field-effect transistor (MOSFETs), particularly when process-induced sidewall inclination ( \(\theta \) ) alters device electrostatics and exacerbates short-channel effects. Despite its significance, no analytical framework exists to model GIDL in trapezoidal GAA structures with non-vertical sidewalls. The model is derived from a quasi-three-dimensional (3D) scaling equation that incorporates an effective scaling length ( \(\lambda _{\text {eff}}\) ), which is expressed using the perimeter-weighted-sum and equivalent number of gates (ENG) technique. This model accounts for various device parameters including channel length ( \(L_g\) ), top width ( \(W_{\text {top}}\) ), and channel height ( \(H_{\text {Fin}}\) ). The side-wall inclination angle ( \(\theta \) ) is varied from \(0^\circ \text{ to } 25^\circ \) to study its impact on surface potential, electric field, and gate-induced leakage current ( \( I_{\text {GIDL}} \) ). The analytical predictions closely match both experimental and technology computer-aided design (TCAD) simulations, validating the modal accuracy. Results indicate that \(I_{\text {GIDL}}\) increases by approximately 1.4 to 2.44 times as \(\theta \) varies from \(0^\circ \) to \(25^\circ \) . Moreover, sensitivity analysis highlights that \(W_{\text {top}}\) exhibits the strongest influence on \(\lambda _{\text {eff}}\) and hence on \(I_{\text {GIDL}}\) . These findings offer valuable insights for optimizing device performance by controlling sidewall geometries and structural parameters.
