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<p>Applying a carbon capping layer during high-temperature rapid thermal annealing is a crucial process for lattice repair and achieving high electrical activation rates in the fabrication of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs). In this paper, batch electrical measurements are applied to thoroughly investigate the impact of the carbon layer on the interface and oxide characteristics of <i>n</i>-type SiC MOS structures. The statistical data conclusively prove that annealing with a carbon layer can improve interface quality and device uniformity, with means and standard deviations of interface state density (at <i>E</i><sub>c</sub> − <i>E</i><sub>t</sub> = 0.2&#xa0;eV) decreasing by 16% and 20%, respectively. With the means of effective fixed charge, breakdown field, and Fowler–Nordheim (FN) tunneling barrier height increasing by 9.9%, 0.3%, and 0.3%, respectively, further positive and laser-assisted negative bias temperature instability (BTI) measurements are employed, and no degradation in reliability is observed. Furthermore, different types of defects (including donor-like and acceptor-like traps at deep energy levels of the interface and near the interface) are characterized by laser-assisted transient capacitance (<i>C</i><sub><i>g</i></sub>-<i>t</i>) and capacitance–voltage (<i>C</i><sub><i>g</i></sub>-<i>V</i><sub><i>g</i></sub>) measurements, where the density of acceptor-like traps decreases by 29% and the density of donor-like traps decreases by 60%, and the corresponding mechanism is also analyzed.</p>

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Comparative Analysis of the Influence of Carbon Capping Layer Annealing on the Electrical Characteristics of 4H-SiC MOS Structures

  • 期刊论文

  • 发表日期：

    2025年7月15日

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  • Kanghua Yu,
  • Wenhao Zhang,
  • Changsha Zhang,
  • Yuwei Wang,
  • Jun Wang

摘要

Applying a carbon capping layer during high-temperature rapid thermal annealing is a crucial process for lattice repair and achieving high electrical activation rates in the fabrication of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs). In this paper, batch electrical measurements are applied to thoroughly investigate the impact of the carbon layer on the interface and oxide characteristics of n-type SiC MOS structures. The statistical data conclusively prove that annealing with a carbon layer can improve interface quality and device uniformity, with means and standard deviations of interface state density (at Ec − Et = 0.2 eV) decreasing by 16% and 20%, respectively. With the means of effective fixed charge, breakdown field, and Fowler–Nordheim (FN) tunneling barrier height increasing by 9.9%, 0.3%, and 0.3%, respectively, further positive and laser-assisted negative bias temperature instability (BTI) measurements are employed, and no degradation in reliability is observed. Furthermore, different types of defects (including donor-like and acceptor-like traps at deep energy levels of the interface and near the interface) are characterized by laser-assisted transient capacitance (Cg-t) and capacitance–voltage (Cg-Vg) measurements, where the density of acceptor-like traps decreases by 29% and the density of donor-like traps decreases by 60%, and the corresponding mechanism is also analyzed.