Scholarlink

<p>As a nano-scale, non-volatile device compatible with CMOS technologies, the memristor is well suited for in-memory computing and provides a new venue for accelerating neural network computing. However, memristor-based neural networks are typically based on continuous-type memristors or binary memristors. Continuous-type memristors require precise voltage amplitude and duty cycle for setting resistance, which increases the difficulty of practical applications, whereas binary memristors provide limited weight accuracy due to their restricted two memrisitance states. In contrast, tri-valued memristors feature three discrete resistance values, enabling them to represent a broader range of weight states and allowing a more straightforward resistance setting mechanism. This leads to a better balance between the hardware feasibility and the weight representation capacity of the artificial neural network. This paper proposes a ternary neural network design scheme based on tri-valued memristors. The design scheme consists of a fully hardware-based forward computing circuit using a tri-valued memristor crossbar array, a tri-valued memristance-based weight setting method, a weight updating algorithm for the ternary quantized neural network, an activation function circuit, and a winner-take-all (WTA) circuit. This design features the natural synaptic characteristics of memristors and the computational advantages of the quantized neural network, facilitating a hardware platform and a feasible implementation scheme for lightweight all-hardware neural circuit design. The scheme verified with LTSpice circuit simulations enables correct recognition of test characters ‘<i>z</i>’, ‘<i>v</i>’, and ‘<i>n</i>’. Furthermore, it is extended to the LeNet-5 network on the MemTorch platform, achieving a recognition accuracy of 98.47% in the MNIST benchmark test.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Ternary quantitative neural network implemented with tri-valued memristors

  • 期刊论文

  • 发表日期：

    2026年4月9日

查看全文
  • Xiaoyuan Wang,
  • Zhilong Li,
  • Xiaolu Lucia Li,
  • Hang Li,
  • Jizhao Liu,
  • Herbert H. C. Iu,
  • Sung-Mo Kang

摘要

As a nano-scale, non-volatile device compatible with CMOS technologies, the memristor is well suited for in-memory computing and provides a new venue for accelerating neural network computing. However, memristor-based neural networks are typically based on continuous-type memristors or binary memristors. Continuous-type memristors require precise voltage amplitude and duty cycle for setting resistance, which increases the difficulty of practical applications, whereas binary memristors provide limited weight accuracy due to their restricted two memrisitance states. In contrast, tri-valued memristors feature three discrete resistance values, enabling them to represent a broader range of weight states and allowing a more straightforward resistance setting mechanism. This leads to a better balance between the hardware feasibility and the weight representation capacity of the artificial neural network. This paper proposes a ternary neural network design scheme based on tri-valued memristors. The design scheme consists of a fully hardware-based forward computing circuit using a tri-valued memristor crossbar array, a tri-valued memristance-based weight setting method, a weight updating algorithm for the ternary quantized neural network, an activation function circuit, and a winner-take-all (WTA) circuit. This design features the natural synaptic characteristics of memristors and the computational advantages of the quantized neural network, facilitating a hardware platform and a feasible implementation scheme for lightweight all-hardware neural circuit design. The scheme verified with LTSpice circuit simulations enables correct recognition of test characters ‘z’, ‘v’, and ‘n’. Furthermore, it is extended to the LeNet-5 network on the MemTorch platform, achieving a recognition accuracy of 98.47% in the MNIST benchmark test.