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<p>This paper introduces an efficient, lightweight, invisible, blind, real-time video watermarking system. Symmetric chaotic key encryption enhances the system’s security, ensuring robustness by randomly selecting pixels or coefficients for watermark embedding. The first-level discrete wavelet transform (DWT) is applied to selected data, embedding the watermark into the low-frequency band (LL sub-band). The approach involves random selection of data for quantization using the quantization index modulation (QIM) technique. The proposed scheme is implemented on a low-cost FPGA board (Zybo Z7-20), using a software/hardware (SW/HW) co-design approach. Experimental results demonstrate high fidelity with a peak signal-to-noise ratio (PSNR) exceeding 35 dB and normalized correlation (NC) around 0.99. The architecture achieves a balanced compromise between low FPGA area with high operational speed up to 127 MHz and minimal power consumption not exceeding 51 mW. Performance evaluation confirms the system’s robustness against various attacks, including filtering, additional noise, geometrical modifications, and contrast adjustments. This makes it highly suitable for real-time embedded video applications where data integrity is paramount.</p>

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Efficient FPGA implementation of chaos-based real-time video watermarking system in spatial and DWT domain using QIM technique

  • 期刊论文

  • 发表日期：

    2025年1月8日

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  • Nour Eddine Aissaoui,
  • Mohamed Salah Azzaz,
  • Redouane Kaibou,
  • Camel Tanougast

摘要

This paper introduces an efficient, lightweight, invisible, blind, real-time video watermarking system. Symmetric chaotic key encryption enhances the system’s security, ensuring robustness by randomly selecting pixels or coefficients for watermark embedding. The first-level discrete wavelet transform (DWT) is applied to selected data, embedding the watermark into the low-frequency band (LL sub-band). The approach involves random selection of data for quantization using the quantization index modulation (QIM) technique. The proposed scheme is implemented on a low-cost FPGA board (Zybo Z7-20), using a software/hardware (SW/HW) co-design approach. Experimental results demonstrate high fidelity with a peak signal-to-noise ratio (PSNR) exceeding 35 dB and normalized correlation (NC) around 0.99. The architecture achieves a balanced compromise between low FPGA area with high operational speed up to 127 MHz and minimal power consumption not exceeding 51 mW. Performance evaluation confirms the system’s robustness against various attacks, including filtering, additional noise, geometrical modifications, and contrast adjustments. This makes it highly suitable for real-time embedded video applications where data integrity is paramount.