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<p>For six decades, Moore’s geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling. This perspective argues for a successor scaling principle—<i>τ</i> scaling—that adopts time itself, rather than transistor area, as the primary metric of progress, applying a single characteristic time constant <i>τ</i> as the unifying optimization target across twelve orders of magnitude, from a switching transistor to a data-center workload. Two production-scale demonstrations are presented. On a mobile SoC, <i>LogicFolding</i>—a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers—delivers a 55% step-wise increase in transistor density and a 41% reduction in power consumption at equivalent performance at a fixed device node. On AI systems, a co-designed stack comprising the memory-semantic Unified Bus fabric, near-packaged Hi-ONE optical I/O, and edge-to-surface 3D Folding projects more than 100× growth in hardware integration by 2035. The deeper claim is methodological: <i>τ</i> scaling is the first scaling principle since Dennard to establish a shared optimization target across the entire computing stack.</p>

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A time scaling theory for multi-layer electronic systems

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年7月21日

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  • Tingbo He

摘要

For six decades, Moore’s geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling. This perspective argues for a successor scaling principle—τ scaling—that adopts time itself, rather than transistor area, as the primary metric of progress, applying a single characteristic time constant τ as the unifying optimization target across twelve orders of magnitude, from a switching transistor to a data-center workload. Two production-scale demonstrations are presented. On a mobile SoC, LogicFolding—a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers—delivers a 55% step-wise increase in transistor density and a 41% reduction in power consumption at equivalent performance at a fixed device node. On AI systems, a co-designed stack comprising the memory-semantic Unified Bus fabric, near-packaged Hi-ONE optical I/O, and edge-to-surface 3D Folding projects more than 100× growth in hardware integration by 2035. The deeper claim is methodological: τ scaling is the first scaling principle since Dennard to establish a shared optimization target across the entire computing stack.