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<p>Low-density parity check (LDPC) decoding is an efficient error correction method in communication systems, especially in 5G networks, which require high performance and low latency; while common generalpurpose architectures cannot meet the requirements. There has been some research on accelerating LDPC decoding, but the current methods still suffer from limitations in performance, flexibility, and communication cost. In this paper, we propose HARLD (Heterogeneous Architecture of RISC-V for LDPC Decoding), a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding, consisting of a CPU and a processing array. Compared with a loosely coupled System-on-Chip (SoC)-bus baseline, the tightly coupled design improves throughput by up to 32.4% and reduces average latency by up to 24.7% across evaluated configurations, while also enhancing resource and energy efficiency: processing element utilization up to 93.5%, instruction RAM utilization increased by up to 4.8x, and energy efficiency improved by up to 24.8%. At the system level, area and power are reduced by 17.6% and 10.2%, respectively, versus the loosely coupled design.</p>

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HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding

  • 期刊论文

  • 发表日期：

    2026年1月21日

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  • Bing Wang,
  • Zi-Rui Ma,
  • Hai-Bin Wu,
  • Fu-Lin Zhang,
  • Yue Wang,
  • Zhi-Hua Fan,
  • Wen-Ming Li,
  • Xiao-Chun Ye,
  • Dong-Rui Fan

摘要

Low-density parity check (LDPC) decoding is an efficient error correction method in communication systems, especially in 5G networks, which require high performance and low latency; while common generalpurpose architectures cannot meet the requirements. There has been some research on accelerating LDPC decoding, but the current methods still suffer from limitations in performance, flexibility, and communication cost. In this paper, we propose HARLD (Heterogeneous Architecture of RISC-V for LDPC Decoding), a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding, consisting of a CPU and a processing array. Compared with a loosely coupled System-on-Chip (SoC)-bus baseline, the tightly coupled design improves throughput by up to 32.4% and reduces average latency by up to 24.7% across evaluated configurations, while also enhancing resource and energy efficiency: processing element utilization up to 93.5%, instruction RAM utilization increased by up to 4.8x, and energy efficiency improved by up to 24.8%. At the system level, area and power are reduced by 17.6% and 10.2%, respectively, versus the loosely coupled design.