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<p>The forward error correction (FEC) is receiving a lot of attention in optical transport networks (OTN) due to its high bandwidth support. Using Bose–Chaudhuri–Hocquenghem (BCH) as the component code, a low power very large scale integration (VLSI) architecture for a staircase (SC) decoder is designed in this work. The configurable pipelining stages and asynchronous control (CPSAC) mechanism controls different functional units’ of BCH decoder in a controlled sequential order with gating of global clock and reset signals. This prevents unwanted switching activity in the functional units that waits for valid data. The performance of the proposed low power CPSAC-SC decoder architecture is compared with existing low power architectures in terms of power consumption, area, delay and throughput. The proposed CPSAC-SC decoder is functionally verified with MATLAB and the VLSI micro architecture is designed using SystemVerilog hardware description language (HDL), simulated in Siemen’s Modelsim and synthesized using TSMC technology with Cadence’s Virtuoso. The total power consumption of 709 mW is obtained at 65 nm, 916 mW at 90 nm, and 931 mW at 180 nm using TSMC technology libraries.</p>

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Design and Analysis of Low Power Staircase Decoder Using Configurable Pipeline Stages and Asynchronous Control Mechanism

  • 期刊论文

  • 发表日期：

    2026年1月31日

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  • Selciya Selvan,
  • M. Bharathi

摘要

The forward error correction (FEC) is receiving a lot of attention in optical transport networks (OTN) due to its high bandwidth support. Using Bose–Chaudhuri–Hocquenghem (BCH) as the component code, a low power very large scale integration (VLSI) architecture for a staircase (SC) decoder is designed in this work. The configurable pipelining stages and asynchronous control (CPSAC) mechanism controls different functional units’ of BCH decoder in a controlled sequential order with gating of global clock and reset signals. This prevents unwanted switching activity in the functional units that waits for valid data. The performance of the proposed low power CPSAC-SC decoder architecture is compared with existing low power architectures in terms of power consumption, area, delay and throughput. The proposed CPSAC-SC decoder is functionally verified with MATLAB and the VLSI micro architecture is designed using SystemVerilog hardware description language (HDL), simulated in Siemen’s Modelsim and synthesized using TSMC technology with Cadence’s Virtuoso. The total power consumption of 709 mW is obtained at 65 nm, 916 mW at 90 nm, and 931 mW at 180 nm using TSMC technology libraries.