Scholarlink

<p>This paper presents a comprehensive study, hardware implementation and Field Programmable Gate Array (FPGA) prototyping of a flexible pipelined Expectation Propagation (EP)-based receiver that can handle BPSK, QPSK, 8-PSK and 16-QAM mappings. The digital receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the four mappings are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, hardware implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture, as well as a significant reduction in clock cycles due to a pipeline approach. Hardware-in-the-Loop (HIL) simulations show similar performance for the FPGA prototype by comparison with the software reference.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Design and FPGA Prototyping of a Flexible Receiver based on Expectation Propagation

  • 期刊论文

  • 发表日期：

    2026年1月6日

查看全文
  • Ian Fischer Schilling,
  • Serdar Şahin,
  • Camille Leroux,
  • Antonio Maria Cipriano,
  • Christophe Jégo

摘要

This paper presents a comprehensive study, hardware implementation and Field Programmable Gate Array (FPGA) prototyping of a flexible pipelined Expectation Propagation (EP)-based receiver that can handle BPSK, QPSK, 8-PSK and 16-QAM mappings. The digital receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the four mappings are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, hardware implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture, as well as a significant reduction in clock cycles due to a pipeline approach. Hardware-in-the-Loop (HIL) simulations show similar performance for the FPGA prototype by comparison with the software reference.