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<p>In modern computer architectures, the performance of many memory-bound workloads (e.g., machine learning, graph processing, databases) is limited by the data movement bottleneck that emerges when transferring large amounts of data between the main memory and the central processing unit (CPU). Processingin-memory (PIM) is an emerging computing paradigm that aims to alleviate this data movement bottleneck by performing computation <i>close to</i> or <i>within</i> the memory units, where data resides. One example of a prevalent workload whose performance is bound by the data movement bottleneck is the training and inference process of artificial neural networks (ANNs). In this work, we analyze the potential of modern general-purpose PIM architectures to accelerate neural networks (NNs). To this end, we selected the UPMEM PIM system, the first commercially available real-world general-purpose PIM architecture. We compared the implementation of multilayer perceptrons (MLPs) in PIM with a sequential baseline running on an Intel Xeon CPU. The UPMEM implementation achieves up to <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\varvec{259\times }\)</EquationSource> </InlineEquation> better performance for inference of large batch sizes when compared against the CPU that exploits the size of the available PIM memory. Additionally, two smaller MLPs were implemented using UPMEM’s working random access memory (WRAM), a scratchpad memory, to evaluate their performance against a low-power Nvidia Jetson graphics processing unit (GPU), providing further insights into the efficiency of UPMEM’s PIM for neural network inference. Results show that using WRAM achieves kernel execution times for MLP inference of under <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(\varvec{3}\)</EquationSource> </InlineEquation> ms, which is within the same order of magnitude as low-power GPUs.</p>

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An Experimental Exploration of In-Memory Computing for Multi-Layer Perceptrons

  • 期刊论文

  • 发表日期：

    2025年11月17日

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  • Pedro Carrinho,
  • Hamid Moghadaspour,
  • Oscar Ferraz,
  • João Dinis Ferreira,
  • Yann Falevoz,
  • Vitor Silva,
  • Gabriel Falcao

摘要

In modern computer architectures, the performance of many memory-bound workloads (e.g., machine learning, graph processing, databases) is limited by the data movement bottleneck that emerges when transferring large amounts of data between the main memory and the central processing unit (CPU). Processingin-memory (PIM) is an emerging computing paradigm that aims to alleviate this data movement bottleneck by performing computation close to or within the memory units, where data resides. One example of a prevalent workload whose performance is bound by the data movement bottleneck is the training and inference process of artificial neural networks (ANNs). In this work, we analyze the potential of modern general-purpose PIM architectures to accelerate neural networks (NNs). To this end, we selected the UPMEM PIM system, the first commercially available real-world general-purpose PIM architecture. We compared the implementation of multilayer perceptrons (MLPs) in PIM with a sequential baseline running on an Intel Xeon CPU. The UPMEM implementation achieves up to \(\varvec{259\times }\) better performance for inference of large batch sizes when compared against the CPU that exploits the size of the available PIM memory. Additionally, two smaller MLPs were implemented using UPMEM’s working random access memory (WRAM), a scratchpad memory, to evaluate their performance against a low-power Nvidia Jetson graphics processing unit (GPU), providing further insights into the efficiency of UPMEM’s PIM for neural network inference. Results show that using WRAM achieves kernel execution times for MLP inference of under \(\varvec{3}\) ms, which is within the same order of magnitude as low-power GPUs.