Application-Specific NoCs (ASNoCs) often lead to better performance, power consumption, and area requirement compared to the state-of-the-art regular Mesh NoCs as they are tailored to suit the communication requirement of the target application. Unlike the regular NoCs, ASNoCs support heterogeneous core sizes with flexible placements of cores, routers, and links. This work has developed and analyzed two constructive heuristic methods for communication cost-aware placement of routers: 1. Core Communication Cost-Centric Heuristic ( \({\text{C}}^{{\text{3}}} {\text{H}}\) ) with correction phases and 2. Weighted Voting by the Neighbors Heuristic ( \({\text{WVNH}}\) ) with Selective Pruning and Constructive Selection phases. A Simulated Annealing (SA)-based router positions fine-tuning technique has also been introduced to further improve the communication cost. Effectiveness of these methods has been assessed using core graphs from multimedia benchmark applications, with analysis based on a set of thousand distinct core floorplans for each application. The proposed techniques significantly improve the communication cost of the chip (in \(MBps \times mm\) ), achieving up to a 42% reduction compared to existing methods. When combined with the SA-based tuning phase, the proposed techniques yield exact results in all experiments while significantly reducing runtime compared to ILP-based approach. Finally, the router placement algorithms developed in this work have been strategically integrated into various stages of the proposed Thermal- and Performance-aware Area-Constrained Planar ASNoC (TPAP-ASNoC) synthesis tool, thereby realizing a unified planar ASNoC design framework that achieves optimized chip area, temperature, and network performance in terms of average packet latency and throughput.
