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<p>High-performance computing (HPC) systems now operate at Exascale, enabling unprecedented computational capability for large-scale scientific and data-intensive applications. However, as these systems scale, communication overhead increasingly limits parallel efficiency. CPU-centric handling of network communication and data movement introduces significant overhead. To address this challenge, SmartNICs have emerged as an important architectural component that offloads communication and data-processing tasks from the host CPU to the network interface. By moving selected operations closer to the network fabric, SmartNICs can reduce CPU overhead, improve data movement efficiency, and support emerging paradigms such as in-network computing. However, effectively integrating SmartNICs into large-scale computing systems introduces several challenges, particularly in establishing efficient memory access and data exchange between the SmartNIC and host applications. In this study, we evaluate different approaches for enabling memory access between the host and SmartNIC, with a particular focus on FPGA-based SmartNICs. Specifically, we analyze how Direct Memory Access (DMA) in FPGA-based SmartNICs and Remote Direct Memory Access (RDMA) in SoC-based SmartNICs support the high-bandwidth data transfers required by distributed computing workloads. Our findings provide guidance for selecting appropriate memory access designs to support in-network applications and reduce communication overhead in large-scale computing environments.</p>

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In-network memory access: bridging SmartNIC and host memory

  • 期刊论文

  • 发表日期：

    2026年5月28日

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  • Mohammed Zain Farooqi,
  • Masoud Hemmatpour,
  • Tore Heide Larsen

摘要

High-performance computing (HPC) systems now operate at Exascale, enabling unprecedented computational capability for large-scale scientific and data-intensive applications. However, as these systems scale, communication overhead increasingly limits parallel efficiency. CPU-centric handling of network communication and data movement introduces significant overhead. To address this challenge, SmartNICs have emerged as an important architectural component that offloads communication and data-processing tasks from the host CPU to the network interface. By moving selected operations closer to the network fabric, SmartNICs can reduce CPU overhead, improve data movement efficiency, and support emerging paradigms such as in-network computing. However, effectively integrating SmartNICs into large-scale computing systems introduces several challenges, particularly in establishing efficient memory access and data exchange between the SmartNIC and host applications. In this study, we evaluate different approaches for enabling memory access between the host and SmartNIC, with a particular focus on FPGA-based SmartNICs. Specifically, we analyze how Direct Memory Access (DMA) in FPGA-based SmartNICs and Remote Direct Memory Access (RDMA) in SoC-based SmartNICs support the high-bandwidth data transfers required by distributed computing workloads. Our findings provide guidance for selecting appropriate memory access designs to support in-network applications and reduce communication overhead in large-scale computing environments.