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<p>Spiking neural networks (SNNs) offer energy-efficient, bio-inspired solutions for computer vision in neuromorphic systems. However, their temporal dynamics and the event-driven characteristic make deployment challenging on resource-constrained hardware platforms. To address the above issue, this paper proposes a hardware-efficient SNN accelerator that leverages architectural techniques such as loop pipelining and array partitioning to optimize latency and resource utilization. The proposed design is implemented using the high-level synthesis (HLS) framework and evaluated on the Indian Sign Language (ISL) dataset targeting a low-cost, low-memory Xilinx PYNQ-Z2 FPGA. The experimental results demonstrate that: (1) Our optimized SNN design attains a 98.03% classification accuracy with an inference latency of 659&#xa0;ms on the ISL dataset and (2) the proposed accelerator consumes only 1.84W of power while maintaining efficient resource utilization, making it suitable for low-power embedded neuromorphic applications.</p>

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Hardware implementation of SNN-based neuromorphic computing architecture for sign language recognition

  • 期刊论文

  • 发表日期：

    2026年4月3日

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  • Rashi Goyal,
  • Mohita Jaiswal,
  • Kartik Khandelwal,
  • Viren Sharma,
  • Jawar Singh,
  • Abhishek Sharma

摘要

Spiking neural networks (SNNs) offer energy-efficient, bio-inspired solutions for computer vision in neuromorphic systems. However, their temporal dynamics and the event-driven characteristic make deployment challenging on resource-constrained hardware platforms. To address the above issue, this paper proposes a hardware-efficient SNN accelerator that leverages architectural techniques such as loop pipelining and array partitioning to optimize latency and resource utilization. The proposed design is implemented using the high-level synthesis (HLS) framework and evaluated on the Indian Sign Language (ISL) dataset targeting a low-cost, low-memory Xilinx PYNQ-Z2 FPGA. The experimental results demonstrate that: (1) Our optimized SNN design attains a 98.03% classification accuracy with an inference latency of 659 ms on the ISL dataset and (2) the proposed accelerator consumes only 1.84W of power while maintaining efficient resource utilization, making it suitable for low-power embedded neuromorphic applications.