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<p>In analog integrated circuits (ICs), placement plays a crucial role in determining the layout performance. The common centroid (CC) structures are widely used to mitigate the impact of process variations. However, most existing approaches focus solely on generating local CC patterns and lack a unified formulation that simultaneously considers CC constraints and other geometric objectives. Moreover, geometry-driven placement fails to explicitly account for performance. To address these issues, we propose an analytical placement framework for analog ICs that incorporates CC constraints and a performance prediction network, and fully exploits GPU-accelerated analytical optimization to achieve placement with second-level runtime per design case. Experimental evaluations demonstrate that the proposed method consistently outperforms manual design and state-of-the-art automatic tools in both layout compactness and post-layout circuit performance.</p>

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WHUTPlace: performance-driven analytical placement of analog ICs with common centroid constraints

  • 期刊论文

  • 发表日期：

    2026年3月14日

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  • Tao Su,
  • Yong Zhang,
  • Xianrong Qin,
  • Xiaoyu Liang,
  • Changhao Yan,
  • Ning Xu,
  • Bowen Jia

摘要

In analog integrated circuits (ICs), placement plays a crucial role in determining the layout performance. The common centroid (CC) structures are widely used to mitigate the impact of process variations. However, most existing approaches focus solely on generating local CC patterns and lack a unified formulation that simultaneously considers CC constraints and other geometric objectives. Moreover, geometry-driven placement fails to explicitly account for performance. To address these issues, we propose an analytical placement framework for analog ICs that incorporates CC constraints and a performance prediction network, and fully exploits GPU-accelerated analytical optimization to achieve placement with second-level runtime per design case. Experimental evaluations demonstrate that the proposed method consistently outperforms manual design and state-of-the-art automatic tools in both layout compactness and post-layout circuit performance.