Scholarlink

<p>This paper proposes DystoHD, a novel area-efficient and end-to-end hyperdimensional computing (HDC) system. By dynamically generating feature hypervectors and reusing position hypervectors within a systolic array architecture, DystoHD eliminates the need for large static base hypervector storage, significantly reducing memory footprint and access overhead. This design allows for the concurrent deployment of encoding and inference modules at a tiny hardware cost. In addition, DystoHD enhances computational efficiency and architectural scalability by exploiting fine-grained parallelism and resource reuse. We evaluate DystoHD using both FPGA implementation and 45&#xa0;nm process synthesis. Experimental results show that compared with prior art, DystoHD reduces the memory overhead by at least 64.2% with similar classification accuracy on several datasets. Compared to prior FPGA-based and ASIC-based HDC hardware, DystoHD reduces the area-delay product by least 62.0% and 40.6%, respectively.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

DystoHD: an area-efficient hyperdimensional computing system with dynamic hypervector generation for memory-constrained devices

  • 期刊论文

  • 发表日期：

    2026年2月9日

查看全文
  • Haoyu Tang,
  • Yirong Kan,
  • Man Wu,
  • Renyuan Zhang,
  • Yasuhiko Nakashima

摘要

This paper proposes DystoHD, a novel area-efficient and end-to-end hyperdimensional computing (HDC) system. By dynamically generating feature hypervectors and reusing position hypervectors within a systolic array architecture, DystoHD eliminates the need for large static base hypervector storage, significantly reducing memory footprint and access overhead. This design allows for the concurrent deployment of encoding and inference modules at a tiny hardware cost. In addition, DystoHD enhances computational efficiency and architectural scalability by exploiting fine-grained parallelism and resource reuse. We evaluate DystoHD using both FPGA implementation and 45 nm process synthesis. Experimental results show that compared with prior art, DystoHD reduces the memory overhead by at least 64.2% with similar classification accuracy on several datasets. Compared to prior FPGA-based and ASIC-based HDC hardware, DystoHD reduces the area-delay product by least 62.0% and 40.6%, respectively.