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<p>As transistor technology advances and miniaturizes, single chips or multiple chips (chiplets) are now able to integrate hundreds to thousands of cores. Networks-on-Chips (NoCs) have become the standard on-chip communication fabric for multi/many-core systems on chip (MCSoC), offering advantages over traditional buses in terms of scalability, parallelism, and power efficiency. Due to these properties of NoC, computations and communications of different layers of deep neural networks (DNNs) can be performed efficiently on NoCs. However, traditional mapping strategies may not be suitable for running DNNs due to the different types of communication patterns, such as communication between layers of DNN and one-to-many and many-to-one communications in fully connected layers. Due to varying communication patterns, it is necessary to map computations for different layers of a DNN in a manner that mitigates the communication bottleneck within the NoC. The goal of this work is to accelerate DNNs running on NoCs while minimizing energy consumption by reducing the computation and communication loads on nodes (cores/routers) and links of NoC. We have mathematically modeled the task-resource co-allocation problem that maps neural networks onto NoC-based multicore systems using mixed integer linear programming (MILP). We propose a new mapping algorithm called neighbor-aware and, for the first time, introduce dragonfly algorithm (DA)-based mapping in NoCs in this work. Additionally, we adapt simulated annealing (SA), genetic algorithm (GA), and tabu search (TS) for faster and more energy-efficient mapping of DNNs onto NoCs. Simulations on our inhouse-developed platform, integrating gem5 with the Garnet NoC model and DSENT for energy estimation, and representative DNN workloads (trained on MNIST and Iris) show that the neighbor-aware algorithm consistently outperforms the SA, GA, DA, and TS algorithms in mapping performance score and energy consumption. However, the SA, GA, DA, and TS algorithms perform comparably on those metrics and occasionally surpass the neighbor-aware algorithm in latency and throughput.</p>

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Mapping models and heuristics for accelerating deep neural networks and designing energy-efficient networks-on-chip

  • 期刊论文

  • 发表日期：

    2026年1月21日

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  • Md Farhadur Reza,
  • Dominik Cloud

摘要

As transistor technology advances and miniaturizes, single chips or multiple chips (chiplets) are now able to integrate hundreds to thousands of cores. Networks-on-Chips (NoCs) have become the standard on-chip communication fabric for multi/many-core systems on chip (MCSoC), offering advantages over traditional buses in terms of scalability, parallelism, and power efficiency. Due to these properties of NoC, computations and communications of different layers of deep neural networks (DNNs) can be performed efficiently on NoCs. However, traditional mapping strategies may not be suitable for running DNNs due to the different types of communication patterns, such as communication between layers of DNN and one-to-many and many-to-one communications in fully connected layers. Due to varying communication patterns, it is necessary to map computations for different layers of a DNN in a manner that mitigates the communication bottleneck within the NoC. The goal of this work is to accelerate DNNs running on NoCs while minimizing energy consumption by reducing the computation and communication loads on nodes (cores/routers) and links of NoC. We have mathematically modeled the task-resource co-allocation problem that maps neural networks onto NoC-based multicore systems using mixed integer linear programming (MILP). We propose a new mapping algorithm called neighbor-aware and, for the first time, introduce dragonfly algorithm (DA)-based mapping in NoCs in this work. Additionally, we adapt simulated annealing (SA), genetic algorithm (GA), and tabu search (TS) for faster and more energy-efficient mapping of DNNs onto NoCs. Simulations on our inhouse-developed platform, integrating gem5 with the Garnet NoC model and DSENT for energy estimation, and representative DNN workloads (trained on MNIST and Iris) show that the neighbor-aware algorithm consistently outperforms the SA, GA, DA, and TS algorithms in mapping performance score and energy consumption. However, the SA, GA, DA, and TS algorithms perform comparably on those metrics and occasionally surpass the neighbor-aware algorithm in latency and throughput.