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<p>Machine learning models underpin critical applications, and their performance hinges on effective hyperparameter tuning, yet exhaustive methods like GridSearchCV are computationally intensive on general-purpose systems. This paper presents a custom FPGA accelerator for the GridSearchCV–KNN pipeline, simulated on an Intel Cyclone V platform. The six-module RTL design features an on-chip unique memory unit, a pipelined Manhattan distance subtractor, and a parallel sorting Distance Memory that tracks nearest neighbors without explicit sorting. A dedicated hardware controller manages hyperparameter grid enumeration and K-fold evaluation entirely in hardware. We introduce ’CV-full’ (Leave-One-Out Cross-Validation) to test our system under the most intensive circumstances. Post-synthesis simulations show average speedups of 1.8<InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation>, 2<InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation>, and about 10<InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> under 5-fold, 10-fold, and CV-full settings, respectively, with a peak of 27.7<InlineEquation ID="IEq4"> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> over a Google Colab server. By minimizing off-chip memory access and explicit sorting stages, our FPGA design offers a special-purpose hardware solution for accelerating GridSearchCV–KNN hyperparameter tuning.</p>

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Accelerating GridSearchCV hyperparameter tuning method using an FPGA-based hardware accelerator

  • 期刊论文

  • 发表日期：

    2025年12月6日

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  • Arian Shahbazian,
  • Mohammadreza Binesh Marvasti,
  • Seyyed Amir Asghari

摘要

Machine learning models underpin critical applications, and their performance hinges on effective hyperparameter tuning, yet exhaustive methods like GridSearchCV are computationally intensive on general-purpose systems. This paper presents a custom FPGA accelerator for the GridSearchCV–KNN pipeline, simulated on an Intel Cyclone V platform. The six-module RTL design features an on-chip unique memory unit, a pipelined Manhattan distance subtractor, and a parallel sorting Distance Memory that tracks nearest neighbors without explicit sorting. A dedicated hardware controller manages hyperparameter grid enumeration and K-fold evaluation entirely in hardware. We introduce ’CV-full’ (Leave-One-Out Cross-Validation) to test our system under the most intensive circumstances. Post-synthesis simulations show average speedups of 1.8 \(\times\) × , 2 \(\times\) × , and about 10 \(\times\) × under 5-fold, 10-fold, and CV-full settings, respectively, with a peak of 27.7 \(\times\) × over a Google Colab server. By minimizing off-chip memory access and explicit sorting stages, our FPGA design offers a special-purpose hardware solution for accelerating GridSearchCV–KNN hyperparameter tuning.