<p>The rapid growth of neural network parameters presents critical challenges for deploying artificial intelligence on edge devices with limited memory and power budgets. Compute-in-memory (CiM) has emerged as a promising approach to overcoming the memory wall by integrating storage and computation. Under a mature complementary metal-oxide-semiconductor (CMOS) technology, the recently proposed hybrid CiM based on read-only memory (ROM) and static random-access memory (SRAM) is a promising way to further improve energy efficiency by cutting off the off-chip weight fetch. This paper surveys ROM-based CiM circuits in various domains and analyzes their efficiency, accuracy, and scalability. We further explore ROM-SRAM hybrid CiM architectures, which balance memory density and flexibility through weight and structural adaptation for efficient fine-tuning and task migration. Further challenges including achieving larger on-chip capacity, scaling to large models, and protecting data privacy are discussed. Finally, we highlight prospects for expanding hybrid CiM architectures to broader edge artificial intelligence applications.</p>