LNBN: layer-flexible non-blocking bypass network-on-chip for accelerating DNN inference
摘要
On-device artificial intelligence has increased the importance of energy-efficient inference in resource-constrained environments. Lightweight deep neural networks (DNNs) reduce computational complexity by decreasing the data dimensionality of layers, leading to reduced data reuse, causing global buffer bottlenecks and inadequate routing flexibility in accelerators. We propose the layer-flexible non-blocking bypass network-on-chip (LNBN) architecture, integrating (1) a configurable non-blocking bypass router that adapts to multicast in large-scale DNNs, and parallel transmission in lightweight DNNs; (2) a flexible conflict-free routing algorithm that minimizes congestion and distinguishes concurrently executable traffic through path allocation based on layer dimensionality; (3) a block-based versatile mapping scheme that enables systematic routing with irregular layer structures and increases data reuse. These techniques significantly improve the performance and energy efficiency of DNN accelerators during inference. LNBN enhances network throughput by 23.35%, leading to an18.36% reduction in inference time and a 22.08% improvement in energy efficiency compared with dataflow-flexible DNN accelerator.