<p>Im2col-based convolution is a widely used technique in deep learning frameworks to efficiently implement convolution operators. However, in batched input scenarios, it suffers from inefficient weight reuse due to large reuse distances, often becoming a performance bottleneck. Particularly for CPUs with cache, large reuse distances of convolution weight data lead to increased memory access latency and degraded performance. To address this issue, we propose a novel batched-data-layout-optimization (BDLO) method. BDLO optimizes the input matrix layouts during the Im2col phase to reduce reuse distances of weight data, thereby enhancing memory access efficiency in batched Im2col-based convolutions. This method improves performance of batched convolutions on CPUs and is available for both <i>NCHW</i> and <i>NHWC</i> data layouts. Experimental results demonstrate that BDLO outperforms the standard batched Im2col-based convolutions implemented in the widely used open-source deep learning framework LibTorch, while the weight matrix size is larger than the input matrix size. Specifically, BDLO achieves up to 1.40<InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11227_2025_7706_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> speedup for the <i>NCHW</i> layout and 1.37<InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11227_2025_7706_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> for the <i>NHWC</i> layout on the Kunpeng 920 CPU (ARM architecture), and up to 1.81<InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11227_2025_7706_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> for <i>NCHW</i> and 2.33<InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11227_2025_7706_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(\times\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> for <i>NHWC</i> on the Intel Xeon Platinum 8260L CPU (x86 architecture).</p>

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Batched data layout optimization for Im2col-based convolutions on CPUs

  • Hongzhi Zhao,
  • Xun Liu,
  • Ruiyang Chen,
  • Chao Tang,
  • Yangyang He,
  • Deyang Wang,
  • Jinxiang Xie

摘要

Im2col-based convolution is a widely used technique in deep learning frameworks to efficiently implement convolution operators. However, in batched input scenarios, it suffers from inefficient weight reuse due to large reuse distances, often becoming a performance bottleneck. Particularly for CPUs with cache, large reuse distances of convolution weight data lead to increased memory access latency and degraded performance. To address this issue, we propose a novel batched-data-layout-optimization (BDLO) method. BDLO optimizes the input matrix layouts during the Im2col phase to reduce reuse distances of weight data, thereby enhancing memory access efficiency in batched Im2col-based convolutions. This method improves performance of batched convolutions on CPUs and is available for both NCHW and NHWC data layouts. Experimental results demonstrate that BDLO outperforms the standard batched Im2col-based convolutions implemented in the widely used open-source deep learning framework LibTorch, while the weight matrix size is larger than the input matrix size. Specifically, BDLO achieves up to 1.40 \(\times\) × speedup for the NCHW layout and 1.37 \(\times\) × for the NHWC layout on the Kunpeng 920 CPU (ARM architecture), and up to 1.81 \(\times\) × for NCHW and 2.33 \(\times\) × for NHWC on the Intel Xeon Platinum 8260L CPU (x86 architecture).