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<p>In recent years, studies on artificial intelligence and high-performance computing have accelerated computations using field programmable gate arrays (FPGAs). High-level synthesis (HLS) is beneficial for implementing algorithms from these fields onto FPGAs as circuits. However, because the circuits generated by HLS are generally larger than those designed with hardware description language, using FPGAs in practice presents challenges regarding resource restrictions. To address these issues, we proposed a reconfigurable virtual accelerator (ReVA) that allows the sharing of resources across multiple FPGAs and enables the implementation of large-scale circuits. In this study, we proposed and implemented a ReVA Simulator. Furthermore, we estimated the execution time when utilizing ReVA and performed evaluations. The evaluation results demonstrate that the ReVA Simulator achieves a fast Fourier transform reduced by 36% compared to execution in C.</p>

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Simulation environment for reconfigurable virtual accelerators using a field programmable gate array development environment

  • 期刊论文

  • 发表日期：

    2025年4月9日

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  • Shunya Kawai,
  • Eriko Maeda,
  • Kazuki Yaguchi,
  • Yasunori Osana,
  • Takefumi Miyoshi,
  • Hironori Nakajo

摘要

In recent years, studies on artificial intelligence and high-performance computing have accelerated computations using field programmable gate arrays (FPGAs). High-level synthesis (HLS) is beneficial for implementing algorithms from these fields onto FPGAs as circuits. However, because the circuits generated by HLS are generally larger than those designed with hardware description language, using FPGAs in practice presents challenges regarding resource restrictions. To address these issues, we proposed a reconfigurable virtual accelerator (ReVA) that allows the sharing of resources across multiple FPGAs and enables the implementation of large-scale circuits. In this study, we proposed and implemented a ReVA Simulator. Furthermore, we estimated the execution time when utilizing ReVA and performed evaluations. The evaluation results demonstrate that the ReVA Simulator achieves a fast Fourier transform reduced by 36% compared to execution in C.