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<p>The continued scaling of CMOS technology has intensified power density and leakage challenges in very-large-scale integration (VLSI) circuits, where thermal effects critically influence reliability and performance. This review presents a thermal-management-oriented analysis of low-power and leakage reduction techniques in modern VLSI systems. It systematically examines circuit, device, and system-level strategies, including power gating, multi-threshold CMOS, FinFET, and emerging nanoscale and heterogeneous technologies. A comparative framework is developed to evaluate these techniques based on leakage reduction capability, thermal impact, area overhead, and scalability. The study further highlights electro-thermal feedback mechanisms responsible for leakage-induced thermal runaway and identifies key limitations in existing approaches. Unlike conventional surveys that list low-power VLSI techniques, this review uniquely integrates electro-thermal feedback mechanisms with leakage reduction strategies and provides a structured comparative framework linking device-level innovations with system-level thermal behaviour. Finally, it outlines future research directions emphasizing electro-thermal co-design, advanced materials, and adaptive thermal control. This work provides a unified perspective to guide researchers in selecting and optimizing low-power techniques for next-generation thermally aware VLSI design.</p>

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A critical review on low-power and leakage reduction techniques in VLSI circuits from a thermal management perspective

  • 期刊论文

  • 发表日期：

    2026年7月8日

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  • Anitha P Bose,
  • N Santhi

摘要

The continued scaling of CMOS technology has intensified power density and leakage challenges in very-large-scale integration (VLSI) circuits, where thermal effects critically influence reliability and performance. This review presents a thermal-management-oriented analysis of low-power and leakage reduction techniques in modern VLSI systems. It systematically examines circuit, device, and system-level strategies, including power gating, multi-threshold CMOS, FinFET, and emerging nanoscale and heterogeneous technologies. A comparative framework is developed to evaluate these techniques based on leakage reduction capability, thermal impact, area overhead, and scalability. The study further highlights electro-thermal feedback mechanisms responsible for leakage-induced thermal runaway and identifies key limitations in existing approaches. Unlike conventional surveys that list low-power VLSI techniques, this review uniquely integrates electro-thermal feedback mechanisms with leakage reduction strategies and provides a structured comparative framework linking device-level innovations with system-level thermal behaviour. Finally, it outlines future research directions emphasizing electro-thermal co-design, advanced materials, and adaptive thermal control. This work provides a unified perspective to guide researchers in selecting and optimizing low-power techniques for next-generation thermally aware VLSI design.