Time–temperature superposition characterization of viscoelastic behavior of a die-attach thin film for ultra-thin stacked chip scale packages
摘要
Ultra-thin stacked chip scale packaging (UT-SCSP) technology has been widely used to package many non-CPU products, such as wireless and communication devices. In this package, multiple thin silicon dice are stacked on top of each other, and a thin layer of die-attach adhesive is applied between two adjacent Si dice. Consequently, the thermal expansion and viscoelastic properties of the die-attach material have an important effect on package thermal stress and warpage development. In this study, the thermal expansion behavior of a thin film die-attach material used for UT-SCSP applications was determined by thermomechanical analyzer (TMA), whereas the viscoelastic behavior was characterized by conducting time–temperature superposition (TTS) experiments using dynamic mechanical analyzer (DMA). From the TTS results, master curves were constructed for both the storage (