Review on warpage mechanisms and control of packaging substrates for large-scale chiplet integration
摘要
Artificial intelligence (AI) and high-performance computing (HPC) are driving an exponential increase in computing power demand. The rapid increase in the scale of chip integration is a core way to improve computing power, resulting in a huge increase in the size of the substrate for chiplet integration. This growth brings significant challenges in controlling substrate warpage, which can severely impact performance and reliability. How to effectively control warpage in large-scale substrates has become a cutting-edge topic and a focus in the field of advanced packaging. This paper reviews the research progress on substrate warpage, mainly discussing the warpage mechanisms and influencing factors, and elaborates on the current state of research regarding substrate warpage behavior. Finally, this paper summarizes existing issues and deficiencies in current research and outlines future directions for high-precision warpage control of substrates.