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<p>In the critical semiconductor wafer manufacturing process, automated defect classification is pivotal for yield enhancement. However, deploying Deep Learning (DL) models on resource-constrained edge devices faces a tripartite dilemma: the prohibitive computational cost of high-accuracy state-of-the-art (SOTA) models, the intrinsic topological blindness of lightweight Convolutional Neural Networks (CNNs) toward structural defects (e.g., scratches), and the poor generalization on rare defects due to extreme data imbalance. To address these challenges, this paper proposes Edge-HFGAT, a resource-efficient framework designed for real-time automatic optical inspection (AOI). In terms of AI innovation, Edge-HFGAT introduces a novel Hierarchical Fusion mechanism that uses a non-lossy Concatenation Fusion architecture to synergize fine-grained local texture features (<i>x</i><sub>local</sub>) with global topological dependencies (<i>x</i><sub>topo</sub>) derived from Graph Attention Networks (GAT). Unlike prior arts relying on complex post-processing, this unified design achieves intrinsic robustness against topological blindness and data imbalance. For practical engineering deployment, the proposed model offers a feasible solution for resource-constrained edge devices without requiring high-end Graphics Processing Units (GPUs). Experimental results on the raw WM-811K test set yield a Weighted F1-Score of 0.9734 and a Macro F1-Score of 0.8562, representing a highly competitive performance profile compared to established benchmarks. Most significantly, thanks to its compact design (1.17&#xa0;M parameters), Edge-HFGAT achieves an ultra-fast inference speed of 369 frames per second (FPS) on a standard Central Processing Unit (CPU), which is 7.6 times faster than ResNet-50. These results confirm that Edge-HFGAT offers an optimal trade-off between algorithmic precision and engineering efficiency for high-throughput semiconductor production lines.</p>

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Edge-HFGAT: a lightweight and robust hierarchical graph fusion network for real-time wafer defect classification

  • 期刊论文

  • 发表日期：

    2026年6月29日

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  • Jiayi Tang,
  • Liang Cao,
  • Guanghui Xu,
  • Menghan Li,
  • Wenlu Wu,
  • Huiru Yuan

摘要

In the critical semiconductor wafer manufacturing process, automated defect classification is pivotal for yield enhancement. However, deploying Deep Learning (DL) models on resource-constrained edge devices faces a tripartite dilemma: the prohibitive computational cost of high-accuracy state-of-the-art (SOTA) models, the intrinsic topological blindness of lightweight Convolutional Neural Networks (CNNs) toward structural defects (e.g., scratches), and the poor generalization on rare defects due to extreme data imbalance. To address these challenges, this paper proposes Edge-HFGAT, a resource-efficient framework designed for real-time automatic optical inspection (AOI). In terms of AI innovation, Edge-HFGAT introduces a novel Hierarchical Fusion mechanism that uses a non-lossy Concatenation Fusion architecture to synergize fine-grained local texture features (xlocal) with global topological dependencies (xtopo) derived from Graph Attention Networks (GAT). Unlike prior arts relying on complex post-processing, this unified design achieves intrinsic robustness against topological blindness and data imbalance. For practical engineering deployment, the proposed model offers a feasible solution for resource-constrained edge devices without requiring high-end Graphics Processing Units (GPUs). Experimental results on the raw WM-811K test set yield a Weighted F1-Score of 0.9734 and a Macro F1-Score of 0.8562, representing a highly competitive performance profile compared to established benchmarks. Most significantly, thanks to its compact design (1.17 M parameters), Edge-HFGAT achieves an ultra-fast inference speed of 369 frames per second (FPS) on a standard Central Processing Unit (CPU), which is 7.6 times faster than ResNet-50. These results confirm that Edge-HFGAT offers an optimal trade-off between algorithmic precision and engineering efficiency for high-throughput semiconductor production lines.