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<p>This paper proposes a discrete-component-based Built-Out Self-Test (BOST) architecture incorporating a high-precision Time-to-Digital converter (TDC) to overcome limitations of high-speed device testing system. The rapid advancement of Wide Bandgap (WBG) power devices—particularly Gallium Nitride (GaN) devices featuring ultra-fast switching characteristics such as 10&#xa0;ps/V fall-time behavior—has created new challenges for mass-production testing. Conventional Automated Test Equipment (ATE) often lacks sufficient timing accuracy and suffers from signal degradation due to the physical separation between the tester and the device under evaluation, making sub-nanosecond measurements unreliable. We introduce a Vernier SAR TDC that achieves an effective timing resolution of 1&#xa0;ps, not by relying on traditional delay-line interpolation but by injecting a Gaussian-distributed dither (GDD) into the comparator threshold voltage (<InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\varvec{V}_{{\textbf {th}}}\)</EquationSource> </InlineEquation>). This controlled noise, generated on-chip by a microcontroller unit (MCU) implementing the Box–Muller transform, statistically subdivides the coarse 10&#xa0;ps quantization step to realize a fine-resolution “vernier scale.” Experimental validation using a commercial GaN gate driver IC (BD2311NVX-LB) confirms that the proposed method accurately measures rise times and ultra-short pulse widths with 1&#xa0;ps resolution and sub-1&#xa0;ps variation. The results demonstrate that GDD-assisted Vernier SAR TDC significantly enhances timing linearity and mitigates nonidealities such as comparator propagation delay variation. This cost-effective and scalable BOST solution provides a practical pathway for high-volume, picosecond-class testing of next-generation high-speed power devices, serving as an alternative to full-custom ICs.</p>

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A 1 ps Resolution Built–Out Self–Test (BOST) Method for GaN Gate Drivers Using Gaussian–Distributed Dither (GDD)

  • 期刊论文

  • 发表日期：

    2026年6月19日

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  • Keno Sato,
  • Masaya Hirakawa,
  • Kenta Suzuki,
  • Haruo Kobayashi

摘要

This paper proposes a discrete-component-based Built-Out Self-Test (BOST) architecture incorporating a high-precision Time-to-Digital converter (TDC) to overcome limitations of high-speed device testing system. The rapid advancement of Wide Bandgap (WBG) power devices—particularly Gallium Nitride (GaN) devices featuring ultra-fast switching characteristics such as 10 ps/V fall-time behavior—has created new challenges for mass-production testing. Conventional Automated Test Equipment (ATE) often lacks sufficient timing accuracy and suffers from signal degradation due to the physical separation between the tester and the device under evaluation, making sub-nanosecond measurements unreliable. We introduce a Vernier SAR TDC that achieves an effective timing resolution of 1 ps, not by relying on traditional delay-line interpolation but by injecting a Gaussian-distributed dither (GDD) into the comparator threshold voltage ( \(\varvec{V}_{{\textbf {th}}}\) ). This controlled noise, generated on-chip by a microcontroller unit (MCU) implementing the Box–Muller transform, statistically subdivides the coarse 10 ps quantization step to realize a fine-resolution “vernier scale.” Experimental validation using a commercial GaN gate driver IC (BD2311NVX-LB) confirms that the proposed method accurately measures rise times and ultra-short pulse widths with 1 ps resolution and sub-1 ps variation. The results demonstrate that GDD-assisted Vernier SAR TDC significantly enhances timing linearity and mitigates nonidealities such as comparator propagation delay variation. This cost-effective and scalable BOST solution provides a practical pathway for high-volume, picosecond-class testing of next-generation high-speed power devices, serving as an alternative to full-custom ICs.