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<p>The enclosed layout transistor (ELT) is a layout technique developed to reduce the sensitivity of CMOS devices to total ionizing dose effects. By having the gate completely surrounding the drain or source, the ELT design avoids the formation of thick field oxide between these terminals, thereby preventing an increase in leakage current when the device is exposed to radiation. However, ELTs pose challenges such as source-drain asymmetry and difficulties in calculating the effective aspect ratio (W/L). Our research has focused on addressing these challenges, leading to the development of a Pseudo-Symmetric (PS) ELT. This new layout aims to improve performance matching between ELTs and conventional transistors with the same effective aspect ratio. In this work, we conducted an electrical characterization of the PS-ELT, comparing its performance with traditional square ELTs and regular two-edge transistors. Additionally, a study of inter-die variability was performed on 25 circuit samples fabricated using a 130&#xa0;nm process. The analysis included calculating the coefficients of variation (CV) and comparing gate leakage and sub-threshold currents. The results show that PS-ELTs demonstrate good agreement in electrical parameters with two-edge devices, with CVs below 5% for all analyzed parameters, suggesting that the ELT layout method does not significantly affect parameter dispersion.</p>

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Variability and Analog Parameter Characterization in Enclosed Layout Transistors

  • 期刊论文

  • 发表日期：

    2025年9月18日

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  • Gustavo P. Platcheck,
  • Guilherme S. Cardoso,
  • Tiago R. Balen

摘要

The enclosed layout transistor (ELT) is a layout technique developed to reduce the sensitivity of CMOS devices to total ionizing dose effects. By having the gate completely surrounding the drain or source, the ELT design avoids the formation of thick field oxide between these terminals, thereby preventing an increase in leakage current when the device is exposed to radiation. However, ELTs pose challenges such as source-drain asymmetry and difficulties in calculating the effective aspect ratio (W/L). Our research has focused on addressing these challenges, leading to the development of a Pseudo-Symmetric (PS) ELT. This new layout aims to improve performance matching between ELTs and conventional transistors with the same effective aspect ratio. In this work, we conducted an electrical characterization of the PS-ELT, comparing its performance with traditional square ELTs and regular two-edge transistors. Additionally, a study of inter-die variability was performed on 25 circuit samples fabricated using a 130 nm process. The analysis included calculating the coefficients of variation (CV) and comparing gate leakage and sub-threshold currents. The results show that PS-ELTs demonstrate good agreement in electrical parameters with two-edge devices, with CVs below 5% for all analyzed parameters, suggesting that the ELT layout method does not significantly affect parameter dispersion.