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<p>3-dimensional integrated circuits (3D ICs) facilitate miniaturization, enhanced bandwidth, reduced power consumption, superior performance, and scalability. Through-silicon vias (TSVs) serve as essential interconnects in 3D integration technology. However, numerous design challenges arise with TSVs. Furthermore, TSVs can significantly contribute to noise throughout the substrate. Consequently, noise coupling from TSVs is regarded as a critical factor in the design of 3D ICs. This paper presents an in-depth analysis of noise induced by TSVs, examining various key design parameters. The performance of structures utilizing carbon nanotubes (CNTs) and graphene as core materials for TSVs was evaluated in terms of noise coupling reduction. Furthermore, the noise isolation effectiveness of a p + guard ring around the signal TSV in 3D ICs is verified using the TSV noise coupling model. The impact of the proposed shielding techniques was evaluated in both the frequency and time domains. Additionally, noise coupling from TSVs to the silicon substrate was examined with various liner materials, such as silicon dioxide (SiO<sub>2</sub>), benzocyclobutene (BCB), Teflon, and Perylene-N. In comparison to traditional copper (Cu)-filled TSVs, the results show that graphene nanoribbon (GNR) and CNT based TSVs greatly reduce substrate and inter TSV noise. While time domain data indicate a decreased peak substrate noise voltage, frequency domain analysis indicates an improvement in forward transmission. Noise isolation is further improved by the addition of a p + guard ring and optimum liner materials. For next-generation 3D ICs, the suggested TSV architectures provide enhanced signal integrity and thermal-electrical performance. Based on the constraints, the results show that a graphene TSV with BCB as the liner material and a p + guard ring offer the best noise reduction between the TSV and the substrate.</p>

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Graphene-based TSVs with BCB liner and p + guard ring: a paradigm for ultra-low noise 3D ICs

  • 期刊论文

  • 发表日期：

    2026年7月16日

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  • Debika Chaudhuri,
  • Hafizur Rahaman,
  • Tamal Ghosh

摘要

3-dimensional integrated circuits (3D ICs) facilitate miniaturization, enhanced bandwidth, reduced power consumption, superior performance, and scalability. Through-silicon vias (TSVs) serve as essential interconnects in 3D integration technology. However, numerous design challenges arise with TSVs. Furthermore, TSVs can significantly contribute to noise throughout the substrate. Consequently, noise coupling from TSVs is regarded as a critical factor in the design of 3D ICs. This paper presents an in-depth analysis of noise induced by TSVs, examining various key design parameters. The performance of structures utilizing carbon nanotubes (CNTs) and graphene as core materials for TSVs was evaluated in terms of noise coupling reduction. Furthermore, the noise isolation effectiveness of a p + guard ring around the signal TSV in 3D ICs is verified using the TSV noise coupling model. The impact of the proposed shielding techniques was evaluated in both the frequency and time domains. Additionally, noise coupling from TSVs to the silicon substrate was examined with various liner materials, such as silicon dioxide (SiO2), benzocyclobutene (BCB), Teflon, and Perylene-N. In comparison to traditional copper (Cu)-filled TSVs, the results show that graphene nanoribbon (GNR) and CNT based TSVs greatly reduce substrate and inter TSV noise. While time domain data indicate a decreased peak substrate noise voltage, frequency domain analysis indicates an improvement in forward transmission. Noise isolation is further improved by the addition of a p + guard ring and optimum liner materials. For next-generation 3D ICs, the suggested TSV architectures provide enhanced signal integrity and thermal-electrical performance. Based on the constraints, the results show that a graphene TSV with BCB as the liner material and a p + guard ring offer the best noise reduction between the TSV and the substrate.