Quantum-dot cellular automata-based approximate CSA and RBS with ultra-low cells
摘要
Quantum-dot Cellular atomaton (QCA) have received considerable interest as a nanoscale computing solution because of its potential for high device density, low power consumption, and lower latency compared to CMOS technology. On the other hand, approximate computing takes advantage of the error tolerance of many applications to achieve lower hardware complexity and power dissipation. In this paper, five single-layer and I/O-accessible approximate arithmetic circuits for QCA are proposed: a full adder (FA), a full subtractor (FS), a full adder/subtractor (FA/S), a carry save adder (CSA), and a ripple borrow subtractor (RBS). The proposed FA and FS circuits require nine cells with 0.01 µm2 area and 0.5 clock-phase latency, while the proposed FA/S circuit requires ten cells with 0.01 µm2 area and 0.5 clock-phase latency. Based on the proposed primitives, the proposed CSA circuit requires 36 cells with 0.04 µm2 area and 0.5 clock-phase latency, while the proposed RBS circuit requires 48 cells with 0.04 µm2 area and 3.5 clock-phase latency. Functional verification is carried out using QCADesigner, and the reported waveforms include the polarization scales (Pmin/Pmax). Robustness is measured in terms of Average Output Polarization (AOP) with respect to temperature variations (T = 1–9 K, step = 2 K), which depicts the expected degradation process while keeping the polarization values within acceptable limits. Furthermore, gate-level QCA cost is measured with respect to four different weighting schemes, and energy dissipation is calculated using QCADesigner-E. The total energy dissipated by the proposed FA/FS is 1.59 × 10−6 eV (Avg_Ebath = 1.44 × 10−7 eV/cycle), whereas the proposed FA/S dissipates 1.76 × 10−6 eV (Avg_Ebath = 1.60 × 10−7 eV/cycle). In summary, the proposed ultra-low-cell-count single-layer structures offer energy-efficient, low-latency.