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<p>In this work, an interpretable hybrid modeling framework is developed that integrates physics-based TCAD simulations, compact Verilog-A implementation, and graph neural network (GNN) analysis to investigate nanoscale Junctionless Gate-All-Around (JLGAA) FETs for ultra-low-power current mirror circuits. The proposed multi-scale methodology couples Silvaco TCAD data with a calibrated Verilog-A compact model, enabling accurate and efficient circuit-level evaluation in the Cadence Spectre environment. The compact model reproduces TCAD characteristics with less than 2.5% deviation, while achieving a &gt; 1000 × reduction in simulation time compared with full 3-D TCAD analysis. An interpretable GNN-based deep learning framework predicts circuit performance metrics, including current accuracy, output resistance, and power consumption, with a mean absolute error below 4% across 900 simulation cases. SHapley Additive exPlanations (SHAP) reveal that channel doping and gate length dominate current matching and energy efficiency. The proposed hybrid TCAD–Verilog-A–GNN methodology provides a transparent, accurate, and computationally efficient pathway for the design and optimization of next-generation ultra-low-power nanoelectronic circuits.</p>

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Interpretable graph neural network framework for ultra-low-power junctionless GAA FET current mirrors: bridging physics-based modeling and circuit design

  • 期刊论文

  • 发表日期：

    2026年1月7日

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  • R. Ouchen,
  • T. Berghout,
  • F. Djeffal

摘要

In this work, an interpretable hybrid modeling framework is developed that integrates physics-based TCAD simulations, compact Verilog-A implementation, and graph neural network (GNN) analysis to investigate nanoscale Junctionless Gate-All-Around (JLGAA) FETs for ultra-low-power current mirror circuits. The proposed multi-scale methodology couples Silvaco TCAD data with a calibrated Verilog-A compact model, enabling accurate and efficient circuit-level evaluation in the Cadence Spectre environment. The compact model reproduces TCAD characteristics with less than 2.5% deviation, while achieving a > 1000 × reduction in simulation time compared with full 3-D TCAD analysis. An interpretable GNN-based deep learning framework predicts circuit performance metrics, including current accuracy, output resistance, and power consumption, with a mean absolute error below 4% across 900 simulation cases. SHapley Additive exPlanations (SHAP) reveal that channel doping and gate length dominate current matching and energy efficiency. The proposed hybrid TCAD–Verilog-A–GNN methodology provides a transparent, accurate, and computationally efficient pathway for the design and optimization of next-generation ultra-low-power nanoelectronic circuits.