This study investigates the scaling behavior of the Dual Interbridge Tree-shaped Nanosheet FET (DIB-TreeFET) for sub-3 nm digital logic applications. Device-level simulations using Sentaurus TCAD explore the effects of varying interbridge thickness (<InlineEquation ID="IEq1"> <EquationSource Format="TEX">$IB_{T}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>I</mi> <msub> <mi>B</mi> <mi>T</mi> </msub> </mrow> </math></EquationSource> </InlineEquation>) from 10 nm to 30 nm and nanosheet thickness (<InlineEquation ID="IEq2"> <EquationSource Format="TEX">$N_{T}$</EquationSource> <EquationSource Format="MATHML"><math> <msub> <mi>N</mi> <mi>T</mi> </msub> </math></EquationSource> </InlineEquation>) from 3 to 9 nm, while keeping other parameters constant. Increasing <InlineEquation ID="IEq3"> <EquationSource Format="TEX">$IB_{T}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>I</mi> <msub> <mi>B</mi> <mi>T</mi> </msub> </mrow> </math></EquationSource> </InlineEquation> results in a 1.71 times improvement in <InlineEquation ID="IEq4"> <EquationSource Format="TEX">$I_{ON}$</EquationSource> <EquationSource Format="MATHML"><math> <msub> <mi>I</mi> <mrow> <mi mathvariant="italic">ON</mi> </mrow> </msub> </math></EquationSource> </InlineEquation>, and similarly, increasing <InlineEquation ID="IEq5"> <EquationSource Format="TEX">$N_{T}$</EquationSource> <EquationSource Format="MATHML"><math> <msub> <mi>N</mi> <mi>T</mi> </msub> </math></EquationSource> </InlineEquation> from 3 nm to 5 nm results in an enhancement in <InlineEquation ID="IEq6"> <EquationSource Format="TEX">$I_{ON}$</EquationSource> <EquationSource Format="MATHML"><math> <msub> <mi>I</mi> <mrow> <mi mathvariant="italic">ON</mi> </mrow> </msub> </math></EquationSource> </InlineEquation> of about 1.58 times. However, both parameters also contribute to less pronounced threshold voltage roll-off, indicating stronger short-channel effects. Optimal device performance is observed at <InlineEquation ID="IEq7"> <EquationSource Format="TEX">$IB_{T}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>I</mi> <msub> <mi>B</mi> <mi>T</mi> </msub> </mrow> </math></EquationSource> </InlineEquation> as 20 nm and <InlineEquation ID="IEq8"> <EquationSource Format="TEX">$N_{T}$</EquationSource> <EquationSource Format="MATHML"><math> <msub> <mi>N</mi> <mi>T</mi> </msub> </math></EquationSource> </InlineEquation> as 5 nm. A CMOS inverter built with this configuration is evaluated under varying VDD, load capacitance (10–1000 aF), and input frequency (1–50 GHz). Key metrics, including propagation delay, power-delay product (PDP), and energy-delay product (EDP), are assessed. A tradeoff point at VDD=0.575 V offers balanced performance. At VDD=0.7 V, the inverter achieves noise margins of 0.29 V (<InlineEquation ID="IEq9"> <EquationSource Format="TEX">$NM_{H}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>N</mi> <msub> <mi>M</mi> <mi>H</mi> </msub> </mrow> </math></EquationSource> </InlineEquation>) and 0.32 V (<InlineEquation ID="IEq10"> <EquationSource Format="TEX">$NM_{L}$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>N</mi> <msub> <mi>M</mi> <mi>L</mi> </msub> </mrow> </math></EquationSource> </InlineEquation>), with a voltage gain of 9.98, demonstrating its suitability for ultra-scaled low-power logic applications.

Scaling impact and performance evaluation of DIB-TreeFET for sub-3 nm digital applications

期刊论文
发表日期：

2025年12月19日

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S. Mounika,
Umakanta Nanda

摘要

This study investigates the scaling behavior of the Dual Interbridge Tree-shaped Nanosheet FET (DIB-TreeFET) for sub-3 nm digital logic applications. Device-level simulations using Sentaurus TCAD explore the effects of varying interbridge thickness ( $IB_{T}$ $I B_{T}$ ) from 10 nm to 30 nm and nanosheet thickness ( $N_{T}$ $N_{T}$ ) from 3 to 9 nm, while keeping other parameters constant. Increasing $IB_{T}$ $I B_{T}$ results in a 1.71 times improvement in $I_{ON}$ $I_{ON}$ , and similarly, increasing $N_{T}$ $N_{T}$ from 3 nm to 5 nm results in an enhancement in $I_{ON}$ $I_{ON}$ of about 1.58 times. However, both parameters also contribute to less pronounced threshold voltage roll-off, indicating stronger short-channel effects. Optimal device performance is observed at $IB_{T}$ $I B_{T}$ as 20 nm and $N_{T}$ $N_{T}$ as 5 nm. A CMOS inverter built with this configuration is evaluated under varying V_DD, load capacitance (10–1000 aF), and input frequency (1–50 GHz). Key metrics, including propagation delay, power-delay product (PDP), and energy-delay product (EDP), are assessed. A tradeoff point at V_DD=0.575 V offers balanced performance. At V_DD=0.7 V, the inverter achieves noise margins of 0.29 V ( $NM_{H}$ $N M_{H}$ ) and 0.32 V ( $NM_{L}$ $N M_{L}$ ), with a voltage gain of 9.98, demonstrating its suitability for ultra-scaled low-power logic applications.