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<p>As VLSI technology scales to sub-7&#xa0;nm nodes, interconnect-related delay and power dissipation become dominant design bottlenecks. This paper presents a comprehensive mathematical framework for modeling and optimizing interconnects in very-large-scale integration (VLSI) systems under delay constraints. Leveraging signal processing theory and circuit-level modeling, we introduce an enhanced delay model incorporating Elmore delay, crosstalk effects, and capacitive coupling. A constrained optimization strategy using Lagrangian relaxation and Karush–Kuhn–Tucker conditions is applied to minimize dynamic power while preserving signal integrity. Simulation results on 7&#xa0;nm process technology demonstrate that the proposed method achieves up to 23% reduction in power with marginal delay overheads. Our framework is validated using HSPICE and Cadence Spectre on standard ISCAS85 and OpenCore benchmarks, providing a practical path to energy-efficient interconnect design.</p>

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A delay-constrained optimization framework for low-power VLSI interconnect design using mathematical signal models

  • 期刊论文

  • 发表日期：

    2025年9月22日

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  • V. Rajkumar,
  • R. Amutha

摘要

As VLSI technology scales to sub-7 nm nodes, interconnect-related delay and power dissipation become dominant design bottlenecks. This paper presents a comprehensive mathematical framework for modeling and optimizing interconnects in very-large-scale integration (VLSI) systems under delay constraints. Leveraging signal processing theory and circuit-level modeling, we introduce an enhanced delay model incorporating Elmore delay, crosstalk effects, and capacitive coupling. A constrained optimization strategy using Lagrangian relaxation and Karush–Kuhn–Tucker conditions is applied to minimize dynamic power while preserving signal integrity. Simulation results on 7 nm process technology demonstrate that the proposed method achieves up to 23% reduction in power with marginal delay overheads. Our framework is validated using HSPICE and Cadence Spectre on standard ISCAS85 and OpenCore benchmarks, providing a practical path to energy-efficient interconnect design.