Efficient and reliable hybrid MTJ/CMOS-based logic-in-memory architecture using SHE-MTJ
摘要
The magnetic tunnel junction (MTJ) offers great potential for the future of logic-in-memory (LiM) computing architecture, owing to its attractive features such as nonvolatility, low static power dissipation, high density, and the ability to integrate in a 3D manner with CMOS technology. However, the stochastic nature of MTJ switching/write operation and associated process variation pose a significant challenge in terms of reliable writing, energy consumption during the writing operation, and bulky write driver. To address these issues, an auto-write termination (AWT) circuit and a write driver are proposed to achieve reliable writing at minimum cost and energy consumption in hybrid SHE-MTJ/CMOS-based LiM architecture. Continuous monitoring of the writing process is facilitated by AWT, wherein stopping redundant write operation and the unnecessary write current flow through the MTJs are prevented. Consequently, it significantly reduces write energy wastage, achieving an impressive reduction of 85% compared to conventional writing (without AWT) and a significant reduction in transistor count compared to the existing work. Furthermore, the AWT circuit effectively prevents redundant MTJ writing, resulting in a substantial enhancement in reliability by reducing the write failure. Therefore, with the incorporation of the AWT circuit, the potential of MTJs in LiM computing architecture is further solidified, as it addresses the challenges associated with their stochastic behavior by enhancing their reliability and promise for future applications.