Modelling and simulation of TSV considering void and leakage defects
摘要
Through-silicon-via (TSV) technology represents a significant advancement in the fabrication of three-dimensional (3D) integrated circuits, enabling the vertical interconnection of chips. This process results in several defects that impact the signal transmission performance of TSVs. This study establishes a unified equivalent circuit model that includes leakage defect TSV, void defect TSV, and defect-free TSV, using a distributed modelling approach. The established equivalent circuit model is then simulated, and its accuracy is confirmed by comparing the S-parameter values with those from 3D electromagnetic simulator simulations. The impact of defects on the transmission performance of TSV signals was investigated by varying the dimension of the leakage factor, the position of the leakage defects, and the voiding factor and void defect position. Additionally, the impact of the coexistence of void and leakage defects on TSV signal transmission performance is investigated.