<p>Approximate computing has emerged as a promising paradigm for error-tolerant applications, enabling power-efficient designs with minimal compromise in output quality. In such applications, division units are often among the most complex and latency-critical components, contributing significantly to overall power consumption. Therefore, approximating the division module offers substantial potential for improving power efficiency. This paper introduces a novel exact divider architecture based on low-power full adders, which achieves reduced power consumption and occupies less area compared to conventional exact divider structures. To further enhance area and power efficiency, three different approximate divider architectures are proposed. These designs apply approximation strategies in three ways: row-wise, column-wise, and a combination of both. All three approximate architectures are implemented using the proposed approximate full adder design. The proposed approximate full adder reduces computational complexity while maintaining a high level of accuracy within the divider architecture. Experimental results demonstrate that the proposed exact and approximate dividers reduce power consumption by up to 20% and 35%, respectively, compared to traditional exact and existing approximate divider architectures, all while maintaining better accuracy. Additionally, the proposed approximate divider achieves up to a 48% reduction in area usage. Evaluation using image processing applications further confirms that the proposed designs outperform existing approximate dividers in both efficiency and output quality.</p>